The Design Of Verification System And Function Simulation Based On Resistance Random Access Memory Chip

With the rapid development of Internet technology and information industry,mass storage researches attract more and more attention.The verification test of memory plays an important role in shortening the development cycle and ensuring the quality of products.Compared with the traditional test method,the automatic test equipment(ATE)of integrated has many advantages,such as good man-machine interface,high degree of automation,easy operation.It has been widely used because it reduces the apply threshold of operation staff.At present the high-end ATE market is monopolized by foreign countries and expensive.In this thesis,developed a economical and practical verification platform based on Resistance Random Access Memory(RRAM)chip functional simulation.The main contents are as follows:1.Have studied the basic principle and testing technology of memory test,and also discussed the research status of ATE at home and abroad.2.To introduce the basic principles of RRAM,study the internal structure and timing principle of the RRAM chip under test,and analysis the function timing in detail.explicitly the test purpose of verification system.3.Introduced the hardware circuit design of verification system based on RRAM chip in detail,including FPGA device selection,pin electronics design,programmable power supply design.4.Mainly introduced the programmable logic design of the verification system,such as ATE communication protocol,the timer logic,formatted waveform design,the diagnostic design and storage design of testing results.5.Finally,the design of the Load Board is introduced,practically test the RRAM chip based on the designed verification system,verified correctness of the system's logic design.The verification system designed in this thesis has the following characteristics:(1)test rate up to lOMhz;(2)custom ATE communication protocol;(3)56 testing channels;(4)independent adjustable timer for each channel;(5)six kind of format encoding;(6)higher cost performance.