RRAM Circuit Design Based On IoT Normally-Off Computing Application

In the normally-off computing applications of the Internet of Things,the processor is not always in working condition.Before the sensor collects data,the processor needs to maintain the standby state.At this time,the logic part of the processor can be turned off by the power management technology.As the on-chip data buffer,the conventional memory SRAM has a certain standby power consumption,so it is necessary to explore new storage solutions.Due to its features such as high speed,high density,low power consumption,compatibility with CMOS technology,non-volatile,etc,resistive random access memory(RRAM)has attracted attention in the normally-off computing applications of the Internet of Things.This paper analyzes and compares different materials and operation types of resistive random access memory devices,based on the resistive properties of HfOx,a binary metal oxide resistive material,an equivalent circuit model for a resistive memory device that can be used for circuit simulation is established at first.This model has only two external ports,in line with the actual number of ports of the resistive memory device;at the same time,this model can simulate the programming operation of the external stimulate performed on the resistive memory device and the read operation after the programming,and contains the resistance property of the resistive memory device.Based on this model,this paper designs an 8Kb RRAM structure and completes the design of the peripheral circuit of the resistive memory array,including the row decode circuit and column decode circuit,read circuit and it's timing control circuit,write driver circuit,reference current source,and bandgap voltage reference,RRAM control logic,etc.The RRAM circuit is simulated based on the SMIC 0.18?m process,and finally achieves an external read and write request to access the RRAM.In order to analyze the power consumption of RRAM in the system,a microprocessor based on RISC-V instruction set was designed.Synopsys DC tool was used to test the power consumption of the processor's logic and SRAM memory.At the same time,the average power consumption of the RRAM during the read and write process was tested by using the Cadence Spectre tool,and then compare the power consumption of the CPU and memory in both systems.The power consumption of the RRAM system is greater than the power consumption of the SRAM system.Comparing the proportion of working time and standby time,when the ratio of the two is 1/600,the power consumption of the RRAM system designed in this paper is reduced by 16.79%compared with the SRAM system,and the power consumption of the RRAM system decreases with the standby time increase.