Composite Buried Layer Soi High Voltage Devices, Numerical Simulation And Experimental Research

Silicon-On-Insulator (SOI) lateral high voltage devices are the key devices in SOI High Voltage Integrated Circuit (HVIC). However, the low vertical breakdown voltage of SOI devices limits the application in high voltage and power integrated circuit. A lot of novel structures have been proposed to enhance the vertical breakdown voltage.A novel SOI high-voltage device with a compound buried-layer (CBL SOI) is investigated in this thesis. The compound buried-layer consists of two oxide layers and a polysilicon layer between them, with a window in the Upper Buried Oxide layer (UBO). Holes are collected on the bottom-interface of the polysilicon because UBO prevents the holes extraction by the lateral electric field in the drift region (or the source). The holes enhance the electric field in the lower oxide layer (LBO), and thus, a high breakdown voltage (BV) can be obtained on the thinner buried oxide layer, resulting in a reduced self-heating effect. On the other hand, the holes layer can also shield the back-gate bias effect on the top Si layer and the UBO. The SOI wafer with the CBL is fabricated by non-equilplanar SOI process. The process of SOI device is simulated by the TSUPREM-4, based on which, a 760V CBL SOI LDMOS is realized. The electric field in LBO for CBL SOI LDMOS is increased from below 120V/μm of the conventional SOI device to 450V/μm.The characteristics of simulator MEDICI and its application in semiconductor devices are introduced. MEDICI is used as the tool for invadiating and studying the breakdown characteristics and back-gate effect in this thesis.