Research Of Fin SOI LDMOS With High-k Dielectric

Lateral double-diffused power MOSFET in Silicon-on-insulator（SOI LDMOS）is widely applied in power integrated circuits due to its easiness to drive,high voltage,high speed,and low parasitic effects.How to achieve high breakdown voltage（BV）and low specific-on resistance(R_on,sp)is one of the main goals of SOI LDMOS design.In recent years,high-k（HK）dielectric has been used in structural design of SOI LDMOS,thereby significantly improving the contradiction between breakdown voltage and specific-on resistance.Based on the application of high-k dielectric in LDMOS,this paper investigates the modulation effect of high-k dielectric at different locations on LDMOS.A new structure of fin SOI LDMOS with integrated triple-direction high-k gate and field dielectric（HKGF Fin LDMOS）is proposed,which is mainly studied from the aspects of device mechanism,structural parameter optimization,process fabrication scheme.The main work includes:（1）The application of high-k dielectric in LDMOS is investigated.According to the position of high-k dielectric in LDMOS,the LDMOS with high-k dielectric is divided to surface HK dielectric LDMOS,sidewall HK dielectric LDMOS,and trench HK dielectric LDMOS.Their structural characteristics,working mechanism,electrical properties,and process fabrication schemes are comprehensive alalyzed and compared.（2）A new structure of HKGF Fin LDMOS is proposed.The main feature of the structure is that the fin-shape active area is surrounded by the three-directional high-k dielectric from sidewall and surface,forming an integrated three-directional high-k field dielectric and three-directional high-k gate dielectric.The new structure has the advantages of high-k field technology,high-k gate dielectric technology,tri-gate technology,and fin technology.In the on-state,the three-directional high-k gate dielectric not only broadens the channel width but also increases the electron concentration of channel inversion layer,thus reducing the channel resistance;At the same time,the capacitor（MIS structure）composed of the metal gate/high-k gate and field dielectric/drift region forms electron accumulation layer on the sidewall and top layer of fin drift region,which futher reduces the resistance of drift region.In the off-state,the three-directional high-k field dielectric assists in depleting the drift region from three directions,thereby optimizing the doping concentration of drift region and obtaining low specific-on resistance;At the same time,the three-directional high-k field dielectric fully modulates the three-dimensional electric field of drift region,thus significantly increasing the breakdown voltage of the new structure.Numerical simulation results show that the breakdown voltage of new structure is increased by 157%and the specific-on resistance is decreased by 48.1%than the conventional SOI LDMOS.Therefore,the new structure achieves a better tradeoff between breakdown voltage and specific-on resistance.（3）A process fabrication scheme of HKGF Fin LDMOS is designed.The process simulation is carried out with Sentaurus process tool.The specific process fabrication parameters are determined and the feasibility of process fabrication scheme is verified by processs sinulation.The process of simulation（Sprocess+Sdevice）results of the HKGF Fin LDMOS are compared with the device simulation（SDE+Sdevice）results under the same structural parameters.The electrical performance of the two is basically the same,which further proves the feasibility of process fabrication scheme and process fabrication parameters.