Optimal Design And Experimental Research Of Lateral High Voltage Devices With MIS Voltage Sustaining Layer

Power semiconductor devices are a type of semiconductor devices that can be used for electrical energy processing,featuring the characteristics of high flexibility and high efficiency.With the application of electrical energy production in human lives more and more widespread,people begin to take efficient management of electric energy into consideration,which means that higher performance power devices are required.However,the trade-off relationship between breakdown voltage V_B and specific on-resistance R_on,sp limits the further improvement of power device performance.Therefore,a variety of optimized designs have been proposed to alleviate the problem.Among them,the junction voltage sustaining layer is the most representative,which improves the V_B of the device by achieving homogenization of electric field;and allows a high doping concentration to reduce the specific on-resistance due to the introduction of a new depletion mechanism,breaking the traditional resistive voltage sustaining layer"silicon limit"relationship.This paper proposes a new type of MIS voltage sustaining layer(MIS VSL)and it is applied to LDMOS(Lateral Double-diffused MOSFET)devices successfully.The main content and results of this project are as follows:(1)A new type of MIS VSL and its analytical model are proposed.In terms of geometric structure,periodically MIS structures penetrated from the surface into the body are introduced into the voltage sustaining layer,forming a periodic body equipotential boundary;in terms of physical mechanism,there is capacitive coupling between adjacent MIS structures,causing leakage voltage is divided equally.And the constant potential difference?V falls between the adjacent electrodes,which is shared by the dielectric layer and the silicon layer.The periodic structure generates a periodic electric field.In addition,there is an adaptive charge balance between the equivalent charge on the MIS electrode and the ionized charge in the withstand voltage layer,so that the heavily doped silicon layer can maintain a low electric field,ensuring high V_B and reducing R_on,sp.A model of the potential field distribution of the MIS voltage sustaining layer is established,which is in good agreement with the simulation results.A design formula of optimal doping concentration range is given based on the optimal field distribution.(2)A LDMOS device with MIS voltage sustaining layer is proposed.Two structure sizes of MIS LDMOS were designed by device simulation.Besides,the optimal concentration range was verified.Then,the process design and process simulation of MIS LDMOS were carried out,and the periodic discrete MIS structure in the body was successfully developed using deep trench etching,oxidation and polysilicon filling technology.The influence of process on the device parameters were explored to determine the fabrication plan.(3)A dielectric termination technology is proposed.This dielectric terminal structure features multiple MIS structure ring surrounding the termination region.Based on the principle of equal voltage division and dielectric withstand voltage in the MIS voltage sustaining layer,the homogenization of electric field is realized,and the electric field at the PN junction near source is lower,which shields the influence of curvature effect on the terminal area.A stable terminal breakdown voltage is realized.In the experiment,the FOM(figure of merit)of the MIS LDMOS device reaches8.41 MW/cm² with the breakdown voltage V_B=669.5 V,and the specific on-resistance R_on,sp=53.3 m?·cm² under the guidance of the design formula.Compared with the Triple RESURF device,under the same V_B,the specific on-resistance is reduced by about 37.4%.The DTT realizes a terminal structure with a terminal length L_T less than the length of the drift region L_d,and the ratio k_T=L_T/L_d can reach a minimum of 0.714,while the DTT structures kept a constant V_B of 600 V with the L_T varying.For the first time,the DTT realized a termination factor k_T<1,which also means a minmum of k_T when compared with the published junction termination technology.