Research And Design On High Resolution Medium Speed Low Power Analog-to-digital Converter

As the feature size scaled down, the advanced process favors the operation speed(bandwidth) of the device. Thus, the low-to-medium speed and medium-to-high resolution successive approximation(SAR) analog-to-digital converters(ADCs) are becoming popular because their highly digital characteristic and low power consumption. On the other hand, the pipelined ADCs are suitable for high-speed and high-resolution applications. But a traditional pipelined ADC consumes much power because it consists of several operational amplifiers(op-amps). A hybrid architecture combines the advantages of SAR and pipelined ADCs attracts much attention in recent years. This thesis researches and implements a 12-bit 50-MS/s two-stage pipelined SAR ADC.This thesis designs a new, hybrid ADC architecture based on Merged-Capacitor--Switching(MCS) SAR and two-stage pipeline architectures. This ADC pipelines a6-bit multiplying digital-to-analog converter(MDAC) with a 7-bit SAR ADC. For the first stage, a “half-gain” MDAC is implemented that reduces the op-amp power and increases its open-loop gain. Use of the SAR architecture for the first stage sub-ADC,instead of the usual flash architecture, reduces power and eliminates the need of a front-end S/H. Furthermore, the use of the SAR architecture for the second stage, helps reduce power and achieve high-resolution, thus eliminating the need for more pipeline stages. This work is designed in TSMC 65-nm 1P9 M CMOS technology. The simulation result shows that the peak SNDR is 70.5738 dB and ENOB is 11.4309-bit at50 MHz sampling rate when input frequency is 9.991 MHz and 1.2-V supply. This ADC consumes 4.91604 mW with 35.6124 fJ/conversion-step figure-of-merit(FoM).