A Design Of 12 Bit Current-steering DAC Based On Gradient Error Suppression Technology

Current steering digital to analog converter (DAC) due to its characteristics of high speed and high drive capability, is widely used in communications, video signal processing, etc. But with the improvement of information processing requirements, high speed and high precision DAC tend to become one of the bottleneck of the whole system. For current steering DAC, the main error source influencing its precision is the random error and gradient error of current source array. Random error will decrease with the increase of a single current source area, and gradient error is increased with the increase of current source array area. Especially with the improvement of current steering DAC resolution, the resolution of the DAC increases by a single bit, the current source array area increases four times, so the gradient error of current source array is become the main factors of its precision .In order to improve the performance of current steering DAC, this paper systematically analyzes the static error sources and dynamic error sources in the DAC,and studied how the error affected the performance of DAC. In particular, to restrain the effect of current source array gradient error on the accuracy, this paper emphatically analyses the relationship between the INL and DNL of current steering DAC and the current source array error, and explores the distribution of current source array error,and Using the rectangle diagonal feature, puts forward a new switch scheme that can eliminates first and second order gradient error, and finally use MATLAB to compare with the traditional switch scheme, verifying the effectiveness of the proposed switching scheme.Based on the proposed new switching scheme, HLMC 55 nm process is presented in this paper, the design is to achieve a 12bit 200 MS/s sampling rate intrinsic precision current steering DAC. The DAC is 6 + 6 segmented structure, the core circuit covers an area of 0.66mm2. Simulation results show that the DNL is 0.05 LSB, INL 0.36 LSB, and for DAC using random walk switch scheme, the DNL is 0.46 LSB, INL 0.42 LSB. This shows the effectiveness of the new switching scheme to improve the precision of DAC.For the DAC Working at 200 MS/s sampling frequency, SFDR at the low frequency(1.56 MHz) is 82.81 dBc, close to the Nyquist frequency (95.3 MHz) is 58.36 dBc. For current steering DAC using Q2 random walk switch scheme , SFDR at the low frequency (1.56 MHz) 81.31 dBc, close to the Nyquist frequency (95.3 MHz) is 50.64 dBc. Visibly, for DAC using the new switching scheme , dynamic performance is also improved.