Research And Design Of High Precision Multi Phase Clock Generator

With the rapid development of integrated circuit technology and science and technology, the requirements of analog signal and digital signal are more stringent, not only in the conversion speed, but also the accuracy and integration. However, analog and digital circuit in the process is not compatible,the development of integrated circuit also meets big challenges.The lower power supply voltage and the process significantly reduced size bring the huge challenge to the integrated circuit industry.Under the inevitable high demand, it is urgent to design a high-performance clock generator to meet the needs of the market industry chain.Firstly, this paper introduces the basic structure and working principle of the delay phase locked loop (DLL), and analyses the small signal model of the equivalent phase locked loop.This paper introduces a delay locked loop circuit, carries on the thorough analysis to the correct thought and structure, including the fractional divider Delta-Sigma modulator .We also research the main sub-circuit analysis and its effect.Then, through the research of the delay phase locked loop, a high precision multi phase clock generator circuit is designed. In order to eliminate the dead zone phenomenon and meet the high frequency signal,the dynamic phase frequency discriminator structure is accepted; to improve the mismatch problem,the structure of charge pump by suppressing current charge pump structure of rail to rail operational amplifier is allowed;based on the sampling theory,a clock correction circuit improves the error correction and delay error optimization between each phase clock , optimizes the performance of the system.At last, the circuit is simulated and verified by 180nm-BiCMOS. The simulation results show that in the 625MHz input clock , the phase difference between the reference clock and the feedback clock is 381.3fs. When the output voltage of the current charge pump is changed in the range of 0.25?1.5 V, the charge discharge current mismatch is about 0.07%. The simulation of multi phase clock generator with correction circuit shows that the phase delay error of multi phase clock is reduced from 71ps to 2PS, and the correction effect is 97%.Under the 1.8V supply voltage, the total power consumption of the clock system is 35.33 mW.