The Design And Implementation Of FFT/IFFT Processor In MB-OFDM UWB System

The Ultra Wide Band(UWB)is one of the most competitive technologies following by the Bluetooth and 802.11a/b among Wireless Personal Area Network(WPAN)transmission technologies.It has the characteristics of large-transmission bandwidth,high-safety,and it can achieve low-power,high-speed transmission in the short distance.Multi-Band of Orthogonal Frequency Division Multiplexing(MB-OFDM)UWB scheme,which uses the time-frequency interleaving,is a classic implement of UWB.The 128 point FFT/IFFT processor is the most complex and important operation module in the MB-OFDM UWB system,consequently,the research and design of FFT/IFFT processor in the MB-OFDM UWB system is of great significance.This paper researches an implementation of the 128-point FFT/IFFT processor in MB-OFDM UWB system.The processor adopts DIT R-(8+16)mixed algorithms.The processor is composed by a parallel R-8 butterfly unit and an 8-road parallel R-16 butterfly unit.It meets the timing requirements of the UWB system and achieves the area and power optimization at the same time.When input data are written into Memory Array(MA),data can go into the parallel R-8 butterfly unit directly after reading in a specific order.After the output of parallel R-8 butterfly unit multiplies by the corresponding rotation factors,the results can be sent to the R-16 butterfly unit directly,and the rotating factors stored by ROMs.The design makes the control signals and input data of idle modules remain the same during the process of RTL code's design in order to reduce unnecessary switches for reducing power consumption.The R-(8+16)mixed algorithms achieves modeling and simulation by MATLAB.By using Verilog HDL to finish hardware implementation,Modelsim to achieve RTL function simulation,and the simulation's results are verified by MATLAB.In addition,this paper also realizes the function of IFFT by conjugating and scaling hardware structures of the FFT processor.The ASIC design of FFT processor are based on the SMIC 0.18um technology library.Design Compiler are used to realize logic synthesis while IC Compiler to realize Floor Plan and Placement.In the process of logic synthesis and layout design,the timing,power and area of FFT processor have been optimized.The consistency check of design is realized by Formality.The extraction of parasitic parameters is realized by StarXtract tools.Prime Time is used to achieve static timing analysis.DRC/LVS check is realized by Calibre.The design of 128 point FFT/IFFT processor in this paper can make data input and output in order.And the output results can be coordinated with other modules in the UWB system directly,the computing delays of data are 17 clock cycles.Under the condition of 1.8 V,25?,the highest rate of processor can be up to 150MHz.Under the frequency of 66.67 MHz,the processor's power is 49.5968 mW,the whole IP core's area is 2903998.9 um2.The processor's control logic is simple,and the plural multipliers and adders have been optimized.The design of ATC is used to storage and extraction of input data,delay units' usage is superior to the traditional delay switch structures,the paper has certain academic value.