Research And Design Of High-performance Wide- Operand Adder Based On FPGA

In digital circuits,the binary adder is the most fundamental arithmetic unit,and is also a key component that limits the performance of various high-performance circuits and systems.Nowadays,with the rapid development of fields such as encryption calculation,the operand bit width of adders becomes larger and larger.For example,the operand bit width of RSA encryption algorithms has reached 1024bits(or 2048bits).Therefore,a high-performance,wide-operand adder structure is urgently necessary,responding to the requirements of fast calculation speed with a small amount of hardware resources.In addition to ASICs,FPGAs have become another common platform to implement digital circuits and systems.At present,foreign and domestic scientists have conducted a lot of research on the design of FPGA wide-operand adders,and have proposed a variety of adder structures,but they have not fully considered the characteristics of FPGA devices.Firstly,this paper studies the design of carry-generation circuit and sum-calculation circuit based on FPGA devices,when the bit width of addition operands is more than several hundred or thousand.Then the paper proposes a new high-performance wideoperand adder structure based on FPGA devices.The main work contents are as follows:According to the storage method of the lookup table LUT and the hardware characteristics of the fast carry chain that the calculation path is from bottom to top,the paper proposes a carry compression structure.In order to reduce the impact of programmable interconnects,the carry generation circuit is based on the method of carry selection and the structure of carry compression.Afterwards,through compared with other traditional carry calculation circuits on FPGA,the experimental results show that the carry-generation circuit not only saves a lot of hardware resources,but also improves the calculation speed.Furthermore,when the bit width of the operand is larger,the performance advantage is more significant.In FPGA devices,the number of interconnecting lines around each configurable logic unit CLB is limited.The sum-calculation circuit is implemented by ripple-carry structure after design and research about FPGA interconnection.In the circuit,the process of summation not only makes full use of the fast carry chain in FPGA,but also there is no need to use an interconnection line for transmitting the carry signal between each block(the adder operands are divided into N blocks).The sum-calculation circuit operates in sequence like a marquee,which greatly improves the performance of the FPGA wideoperand adder.Finally,it is carried out to implement the structure proposed in the paper for functional verification.In general,the FPGA wide-operand adder structure not only consumes less hardware resources,but also has a faster calculation speed.In order to illustrate its performance advantages,the adder proposed in this paper and three typical adder structures(ripplecarry adder,carry-select adder,and improved ripple-carry adder)are implemented in FPGA for performance comparison under different operand bit widths from 200 bits to 2000 bits.,the experimental results show that the proposed wide-operand adder has higher overall performance,compared with other wide adder structures.When the bit width is 2000 bits,the operation delay of the circuit structure is only 11.414 ns,which is only onethird of the improved RCA structure,four-fifths of the CSA structure.