Design Of 65nm-technology-based CMOS 10GHz Carry Look-ahead Adder

In high-performance microprocessors and DSP processor, the adder computing time is of the essence. Basically, the Adder computing are often in the critical path of high-performance processors computing components, especially ALU adder plays a decisive role of the speed for computing time in the processor. Along with the speed booming of microprocessors, the high demand of high-speed adder comes to the Technical and market staff table. Over the years, people put forward a number of rapid adder structure model, and Raised different types of circuit design to realize them. Commonly used algorithm of parallel adders is Carry Look-ahead Adder(CLA) algorithm. To further enhance the adder computational speed, many CLA algorithm variants have been put forward. Being with the increasingly high performance targets, the use of CMOS technology to design and implementation of CLA has become more widespread.Firstly, this assignment introduces several basic types of adders, as well as its working principle, and then focus on the analysis of the structure of CLA, CLA structural parameters, as well as its working principle. This assignment present three improved CLA's the algorithm and the working principle, also introduced the CLA structural parameters factor of CLA constraints for speed improvement, as well as the knowledge of CMOS technology.This assignment present one type of design for 65nm-technology-based CMOS 10GHz CLA, with the focus on the analysis of its working principle, and system architecture. The simulation experiments show that the use of advanced technology 65nmCMOS designed 2-bits CLA working speed can reach 10GHz. And in the same process, the optimization of the circuit configuration can also increase their speed.