Low-Power Mixed Logic Circuit Design

With the development of integrated circuit, the scale of integrated circuit is more and more big, the integration is higher and higher, the performance of the large scale integrated circuit decides the performance of electronic devices. At present, the mobile terminal electronic equipment for IC chip performance requirements more and more strict, with the process of technological progress, more and more kinds of leakage current, the leakage power consumption accounts for the proportion of total power consumption is more and more big, so the design of high speed low power integrated circuit chips has become the inevitable trend of the integrated circuit industry development.Add operation is the most basic arithmetic logic operation in digital electronic system, addition is a basic arithmetical operation in almost all of the equipment, it is often applied to various adder carry in the critical path, and one of the important factors that affect the electronic equipment performance. This paper introduce several adders, based on serial carry adder, linear carry adder, carry look-ahead adder, Manchester adder, such as study, analyses the basic principle and carry the critical path logic reverse it.This paper presents a comprehensive research of traditional low-power CMOS integrated circuit adders, and summarizes the advantages and disadvantages of traditional adders, on this basis, we design the novel 4-bit carry-lookahead adder and novel 4-bit bootstrapped adder by improving algorithm and circuit topology. All full adder cells are simulated by HSPICE based on 130 nm CMOS technology,Four sets of frequencies and four different load capacitances. Take speed, power and power delay product into consideration as reference index, we making a comprehensive comparison and analysis of circuit, respectively. The comprehensive simulation shows that PDP of the novel 4-bit carry-lookahead adder circuit is improved up to 70%-72% and 64%-66% as compared with ripple carry adder circuit and carry-lookahead adder circuit, respectively. The PDP of the bootstrapped adder circuit is improved up to 5%-45% as compared with other adders. From the experimental data, excellent performance of the novel 4-bit carry-lookahead adder and novel 4-bit bootstrapped adder has been further demonstrated. The simulation results of this research are expected to help designers to select the appropriate full adder cell that satisfies their specific applications.