Design And Implementation Of The FPU In X Microprocessor

In this paper, the Floating-point unit of X microprocessor which can finish the operations of single-precision or double-precision floating-point numbers is designed and implemented. The realization of the FPU uses a parallel architecture which is made up of one MAC data-access and one Division data-access. Three full pipeline structure was used in the design of the former, which is mainly merged of a adder and a multiplier. Sixteen single pipeline structure is used in the implemention of the latter, which is formed of a 16 SRT divider. Through the two data-accesses, 28 floating-point instructions are realized, includeing the floating-point addition instruction, floating-point reduction instruction, floating-point multiplication instruction, floating-point division instruction, floating-point load instruction, floating-point store instruction etc.During the design of the MAC data-access, the idea of two-path adder and the technique of special value judgment are combined, the index processing and the mantissa processing are executed parallely in the first pipeline. At the end of the first pipeline, the control signals for latter pipiline can be gained. In the actual design procession, the traditional single-path adder is optimized by computing the zero number of the mantissa, moving operands, adding "1" impliedly, suming the pieces of the product of two numbers by Wallace compressor parallely and other means. The fasionable serial SRT-16 divider is improved by selecting all 4-bit quotient numbers at the same time on the base of studying the algorithm and the implementation structure of the traditional SRT-4 division.the FPU throughed the test of IEEE-754 standard vectors and assembled test vectors which is made up of the special operations of each instruction and the boundary datas and the datas which are carefully selected from a large number of random numbers. At the same time, the simulation-test was implemented in module level, in struction level and in system level to ensure the full of the test and the correctness of the design. The results of DC shows that the speed of the FPU designed speeds up to 1.96ns on the condition of point 13 art in the RTL code level.