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The Design And Optimization Of A Bi-Directional Non_Blocking Ring Architecture

Posted on:2016-05-23Degree:MasterType:Thesis
Country:ChinaCandidate:S F XingFull Text:PDF
GTID:2348330509960555Subject:Software engineering
Abstract/Summary:PDF Full Text Request
Along with the development of the integrated circuit processing technique, more and more IP cores are integrated in a single chip. The demand of the inter-core communication is more and more big. Network on chip becomes the main interconnection structure. The ring network is widely used in chip design, because of the following advantages, including simple design, easy industrial realization and fixed transmission delay and so on. Point to the design requirements of the twelve cores of an X-DSP chip, this paper has designed a high bandwidth and low latency ring network architecture. This article has finished the study as below:1) This article has designed a bi-directional multi-channel and non-blocking ring configuration. It includes five links. One is used for configuration request and the other four are used for read and write request. Then read and write request can transmit to opposite direction on different links. It has been proved that the link utilization of this kind of ring configuration has reached up to 99%. As the link power consumption proportion is too heavy, the data which would be poured into the ring was dealt by low power consumption encoding. After verification, the link power consumption has reduced almost 9%. So it improved the performance of the whole network.2) This paper proposed a kind of out-of-order-output buffer. Compared with the Design of Network Interface by virtual channel technology, this design of the structure reduced 45% in area and 19% in power consumption. Besides, the long interconnection line in the Design of Network Interface can cause timing problem. This paper adopted pipeline timing sequence optimization technology and wire retiming to optimize the timing sequence. According to the comprehensive results, the optimized design resolved the tension of timing, as well as reduced 19% of the combinational logic and 44% of the comprehensive time.3) This paper adopted a verification based on the coverage and assertion to do the test. It finally proved the correctness of the design via building a complete test bench. According to the test results, the function coverage reached 100%.The code coverage reached 96%. So the design satisfied the design requirement.
Keywords/Search Tags:Ring Network, Timing optimization, low power coding technology, coverage verification
PDF Full Text Request
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