Design And Verification Of A Ring Interconnection Network-on-chip

Development of semiconductor process technology,so that the on-chip interconnection network(Network on chip,NOC)as a more mature on-chip interconnect,it has been applied to a wide range of multi-core and many-core systems.The interconnection requirements of a multi-core processor based on a project,this article has designed a multi-link and non-blocking ring interconnect on-chip architecture,have a part of a ring transmission network,a dedicated network access controller and a equipment state control center,the design work mainly includes the following parts:1.Multi-link and non-buffer ring transmission network,including long transmission link and routing node.According to the different types of transaction,the transmission link includes two clockwise transmission read/write link,two anticlockwise transmission read/write link,a one-way transmission configration link.Unbuffered routing node don't block the online message,packets can through the hop link and routing node by one cycle.Setting different link for different types of things can reduce effect of low transaction for high-speed data transmission,and improve the operation efficiency of key performance program.Unbuffered,non-blocking architecture ensures real-time packet transmission.Single cycle through sexual reduces transmission delay.2.Multi-port network access controller,according to the type of transaction is divided into data and configure network access controller.Its pivotal design mainly includes cross clock domain conversion,arbiter design and cache design.Multi-port design allows store and forward of multiple devices.The classification of network access controller to ensure that the different transaction requests independent transmission,without disturbing each other.3.Congestion mechanism use end-to-end star transmission structure,according to a fixed number of beats broadcast device status information to every node.Congestion star structure have simple realization and fast transmission.4.According to the function of network access controller use verification methodology based on UVM mechanism,according to the function of ring transmission network and equipment state control center use traditional orientation test and IFV verification,the verification results show that the design function is correct,and coverage rate is above 95%.In the 45 nm process,the logic synthesis of design results show that this design have reached the design requirements of chip main frequency for 1.5GHz.At last,performance analysis for ring interconnection on chip architecture,the result show that the impact of cache resources on network throughput is small and on network delay is obvious,we need a comprehensive consideration for design.