Thermal-Aware Crosstalk And Delay Of Nano-scale CMOS Interconnect Line

As the CMOS integrated circuits developing into nanometer level, the integrated devices and the metal interconnects scaling down unceasingly, and further increases of the current density as well as the number of layer of metal interconnect line, thermal issues of the interconnects have became a major design considerations for high-performance integrated circuits including microprocessor. The excessively high temperature and the non-uniform thermal profile of interconnects may degrade performance and reliability of ICs, Regarding the complex interconnect network of nanometer level system chip, the effect of parasitic capacitance and parasitic inductance is prominent day by day, and the signal integrity of the interconnects is greatly influenced by the movement of the parameters of the integrate circuit process, so it is necessary to consider the influence of multilevel interconnect layout and the interconnect self-heating effect on the delay and crosstalk.First of all, the paper analyzes the development and trend of the interconnect technology, study the method of interconnect parameters and modeling, and using the model we get the parameters of different type interconnects of 65 nm CMOS process. Base on the thermal model of single interconnect and the actual thermal condition of the multilevel interconnects, this paper propose a kind of novel analytical model of multilevel interconnects, and based on this model we get the thermal profile of ten level Cu interconnects of 65 nm CMOS process.Base on the proposed temperature distribution model of multilevel interconnect, an analytical crosstalk model for the distributed RLC interconnect considering effect of thermal profile is derived. Based on the 65nm CMOS process, we compare the proposed RLC analytical crosstalk model to the Hspice simulation results of different interconnect coupling conditions, and the absolute error is within 6.5%.Finally, base on the multilevel interconnects temperature distribution model and the RLC interconnect delay model of integrate circuit, the paper proposed a novel RLC interconnect delay model considering the thermal profile of multilevel interconnects with the method of numerical analysis, this analytical model has summed up the influence of the configuration of multilevel interconnects, the via heat transfer and self-heating effect on the interconnect delay, which is closer to the actual situation. Delay estimation show that the proposed model has highly precision within 6% errors for global interconnects base on the 65nm CMOS interconnect process, which can be applied in nanometer CMOS system chip computer-aided design.