Analysis Of Nano-scale Interconnect Delay And Crosstalk Considering Process Variations

As the feature size of CMOS integrated circuit enters into the nano-scale phase,the interconnect performance has become a key factor restricting the design ofintegrated circuits. In nanometer technology, the process variations with random naturewill directly result in changes in the physical structure of integrated circuits, therebyaffecting the interconnect performance, which significantly affect integrated circuitfunctionality and performance. To effectively analyze impact of process variations oninterconnect performance, the impact of interconnect process variations on theinterconnect delay and crosstalk noise in VLSI is studied and discussed in thethesis.The approximate function relationships are obtained by analyzing the impact ofinterconnect geometric parameters variations on the interconnect parasitic parameters.On the basis of these studies, the statistical RC interconnect delay model, RLCinterconnect delay model and crosstalk noise model are successfully proposed andbuilt respectively. The mathematical expressions of mean and standard deviation ofinterconnect delay and crosstalk noise can be obtained by using the proposed models.The statistical-delay methodology proposed in the previous section can be easilyextended to include ramp-input waveforms.The computation results show that the timeof calculation is greatly shortened with a good calculating precision using the methodproposed by author as compared to the widely used Monte Carlo method. It is provedthat the method proposed by this paper have high efficiency and are accurate enough,so our models are more practical.Finally, crosstalk aware bandwidth estimation methodhas been proposed in the presence of both inductive as well as capacitive coupling. Thecalculated bandwidth has been compared with the results obtained from that of Spicesimulation. The simulation shows the accuracy and validity of the proposed method.