Delay Analysis And Optimization Of Long Interconnect In High Performance Processor

The history of the progress of integrated circuit technology is the progress of semiconductor process nodes.From 28 nm in 2016 to the beginning of sales of 5nm chips this year,the size of interconnections on digital integrated chips and the distance between them continue to decrease,the number of layers of interconnections within the chip also continues to increase,and the clock for circuit operation frequency continues to increase.The continuous reduction of semiconductor process nodes has brought many new problems to the back-end physical design of digital integrated circuits.Among them,the closed clock has become one of the important problems facing.In the problem of timing convergence,the timing problem of interconnects becomes more and more important.When the process characteristic size reaches the nanometer level,due to the crosstalk noise caused by the coupling capacitance between the interconnects and the increase of the intrinsic delay of the interconnect itself,the interconnect delay has exceeded the logic unit delay and has become the key factor of the total delay of the left and right chips.Therefore,in order to better meet the requirements of timing convergence of highperformance chips,timing analysis and optimization of interconnects have important practical significance.With the increasing of chip integration function and chip area,there will be a large number of long-distance connections,which will cause great constraints on timing convergence,especially for critical path.The global bus in the chip refers to the long-distance bus on the top of the chip.Because of the long interconnection distance and the large number of signals,this kind of bus becomes one of the keys to the timing convergence of the whole chip.In this thesis,we study the interconnect delay optimization of high-performance processor in 28 nm process.The main research contents are as follows:1、This thesis briefly introduces the interconnect classification in the chip,highlights the importance of the top layer long interconnect,theoretically analyzes the simple model of the top layer long interconnect delay,explains the impact of adding buffer on the interconnect delay;analyzes another important source of interconnect delay,namely crosstalk noise,analyzes the generation of crosstalk and discusses the possible solutions to reduce the crosstalk noise.2、According to the requirements,a reasonable electric ground grid is designed.The simulation results show that the grid meets the constraints.VDD(IR-drop)is 3.02%,VSS(IR-drop)is 3.6%,which are all lower than 5% of the requirement.The designed grid is used to supply power to the chip and is also used as the simulation environment for subsequent experiments.3、Design the long line delay experimental scheme and steps;repeat the experiment,collect relevant data,and then analyze the data,summarize the relationship between the metal layer and the metal layer width,wiring density and delay,get the wiring scheme table of each metal layer,and analyze the influence of inserting buffer and shielding wire on crosstalk and interconnect delay with data It is used to guide the long line routing planning and routing optimization of the top level,and to guide the global layout planning of the global engineer.It can also give more precise timing constraints to the underlying module engineers.