Analysis And Optimization Of Interconnect Crosstalk Noise And Delay Based On32nm CMOS Technology

As the CMOS integrated circuits developing into nanometer process, the size andspace of interconnect is continuously decreasing and the number of layer of metalinterconnect line is continuously increasing as well as the chip operating frequency,the crosstalk noise between the adjacent interconnect line and interconnect intrinsicdelay have become critical factor for circuit performance and reliability. For thecomplex interconnect network of nanometer level system, the effect of parasiticcapacitance and parasitic inductance is increasing prominent, the change of theparameters of the integrate circuit process has greatly affect the signal integrity of theinterconnects, so it is important to establish efficient and simple models to getthe value of the crosstalk and interconnect delay, which can provide a reference for ICdesigner and avoid timing and logic error in high speed CMOS design. It also canoffer excellent advantage for the exploitation of EDA software.This paper combining the interconnect performance of nanometer processanalysis and research the development and tendency of interconnect technologyespecially in extracting parameter, building model and some problems of crosstalknoise and delay of interconnect. For the interconnect line of32nm CMOS process size,this paper has carried on the analysis and optimization of crosstalk noise and delay. Itgive the optimization size according to contract the crosstalk noise and delay ofdifferent size.This paper concentrates on the basic parameter of interconnect line and workingmechanism in nanometer integrated circuit. According to this, we get the express ofinterconnect resistance, capacitive and inductive. Considering the effect ofintroducing copper process and low-k dielectric on interconnect models and thecorrelation of frequency to interconnect parameter. For coupling crosstalk noise ofinterconnect, it analyze the mechanism of crosstalk noise. In the base of Devgancrosstalk noise model and Martin crosstalk noise model, considering interconnectinductance we introduce a new RLC crosstalk noise estimation model. A newtransmission line model was proposed and compared the results with HSPICE showthe accuracy. For the interconnect delay, we introduced the traditional Elmore delaymodel, fitted Elmore delay and improving Elmore delay model. Finally, we investigate the interconnect delay variation caused by crosstalk noise. For Capacitivecoupling between interconnect lines, it lead to pattern-dependent delay is analyzed byswitch factor technique from Elmore delay definition. For Inductive coupling betweeninterconnect lines, is also calculated by ABCD matrix method that establishes theRLC interconnect electrical equation. Then interconnect delay expression can beacquired by mathematical optimization and Pade reduced-order technique.