Research And Design Of Passive High Data-rate HF RFID Chip And Key Circuits

The application area of HF RFID(Radio Frequency Identification) technology continuously expands in recent years, and it's gradually integrated with sensor technology, biological medical technology and Internet of Things technology. Constantly emerging complex applications request greater volumes of data and higher data-rate of the HF RFID tags, thus there is a wide application prospect for high data-rate HF RFID tags. This paper studies the passive high data-rate HF RFID tag chips, and designs the rectification circuit, regulating circuit, and charge pump PLL(phase locked loop) with UMC 0.18 ?m Embedded EEPROM 1.8V/5V 2P6 M LLP process.Firstly, this paper analyzes the ASK modulation of the traditional HF RFID system(ISO/IEC 15693, ISO/IEC 14443 Type A/B standard), which constrains the improvement of the data-rate, and proposes a method using segment-circle 8PSK modulation to achieve high data-rate HF RFID, then designs the architecture of the passive high data-rate HF RFID tag chips.Secondly, a NMOS gate cross-connection rectifier is designed, with the PCE(power conversion efficiency) of 47.54%. In addition, a LDO regulator with low power consumption is designed to generate a stable power supply voltage of 1.8V, while the maximum load current is 1 mA, the static current without load is less than 2 ?A, the Load Regulation is less than 3%, the Line Regulation is less than 0.5%, the temperature coefficient is 538.4ppm and the value of PSR at low frequency is-50 d B.Finally, a two-type third-order charge pump PLL in the clock signal generating circuit is designed using Top-Down method. The research of the loop characteristics in the PLL is done by mathematical modeling with MATLAB and behavioral modeling with Verilog-AMS. The dead zone of the PFD is eliminated by adding delay cells in the reset path, the bootstrapping method is adopted to achieve well charge and discharge current matching of the charge pump, and a full swing low-noise ring VCO is realized with cross-coupled differential delay cells. The designed charge pump PLL is simulated, and the simulation results show that the PLL could work well providing a clock signal which is synchronous with the 13.56 MHz input reference signal, while the locked time is about 4?s, the average power consumption is 0.918 mW and the phase noise is less than-130dBc/Hz at 1MHz offset.