High Efficiency And Low Noise Charge Pump Design Study

A high-efficiency low-noise charge pumping DC/DC converter is analyzed in this paper and the chip was taped-out successfully by using 0.5um CMOS process with wide input voltage range of 2.7V to 4.5V to generate high output voltage precision 5±4%V. With the "linear"modulation technique, no inrush current generates when chip starts up and the supply current is no more than 1μA when user disables the chip. This converter can operate normally in the temperature range of -40℃to 85℃according to the design data. The author gived principle analysis based on topology of charge pump DC/DC converters, and designed the whole diagram chip and sub block.Typical sub block was analysised such as: Error Amplifier,Oscillator,Bandgap Reference etc.And improvement was proposed based on their application in high efficiency low-noise charge pump DC/DC converters. Based on the charge pump principle analysis and circuit design in the beginning chapters, the author simulated all the sub block circuits and whole chip circuit by applying EDA tools HSPICE and CADENCE, the simulation result indicates that the IC has achieved the expectation, both function target and electrical characteristics. In circuit design, a novel high-efficiency charge pump with Pulse Frequency Modulation(PFM) control is proposed in this paper. Compared with the conventional linear control charge pump, the PFM control charge pump offers lower quiescent current, higher efficiency and low output ripple, especially in low load condition. After completing circuit simulation, Layout and Post-layout Simulation, we taped-out the chip successfully in famous Foundry abroad and completed test.. Test result proves the function of the chip.