Improvement Of The Clock Frequency Of X86 CPU Core Base On Genus

Circuit synthesis plays an important role in the process of designing VLSI chips.The synthesis strategy affects the quality of the synthesis netlist in all aspects.In the past ten years,with the process entering into the deep sub-micron level,the large difference between the front-end and the back-end has become an important factor restricting the quality of chip design.In the past engineering practice,the interconnect delay in the synthesis phase was idealized or normalized,but the drawbacks of this method began to appear.Moreover,the traditional logic synthesis often did not consider the location information of the unit,as a result,some integrated strategies which need physical information can not be realized well,resulting in the deterioration of WNS index and the decrease of clock frequency.In addition,the optimization of critical path is another important factor to be considered to further increase the effective frequency of the chip.There is a X86 CPU soft core based on TSMC 7nm process.This paper uses the integrated software platform Genus of CADENCE company,aiming at the problems of the integrated CPU chip in the advanced technology,such as the decrease of the quality of the netlist,the increase of the delay and the difficulty of the key path convergence,which are caused by the mismatch of the front and back tools,this paper studies the problems of the integrated CPU chip in the advanced technology,the integrated strategy and the key path optimization scheme suitable for the design are obtained.The main contents of this thesis are as follows:Firstly,according to the traditional logic synthesis method,a set of time priority synthesis strategy is proposed,it includes four key points: disabling SVT,LVT,constraining large fan-out,disabling large fan-in multi-bit flip-flop which is easy to cause local winding block,constraining combined flip-flop to act according to the principle of time sequence priority.The research network found that when performing complex actions such as merge triggers that require reference to location information,there is a big difference between the merging rate of triggers and the average bit number of triggers in the synthesis netlist and the corresponding index of the placement netlist.The reason for this is that the back-end design tool does not recognize the merge decision made by the composite tool and remakes it.On the other hand,idealizing the interconnect delay in the synthesis phase makes the delay estimation too optimistic,leaving some critical paths undiscovered in the synthesis phase,and exposing them only after the cells are laid out,this makes it more difficult to optimize these paths.Then,in order to solve the problem of time series variation caused by the mismatch of front and back end network tables,a set of time series priority physical synthesis strategy is proposed based on the comparison of the two physical synthesis methods.First of all,according to the CPU chip internal module data flow to complete the layout design of the chip,and save with DEF format file.Then,on the basis of the time sequence priority synthesis strategy in the logic synthesis scheme,the physical information in the layout and the physical information in the process are introduced to complete the physical synthesis.The experimental results show that the combination index of each trigger in the synthesis netlist is basically the same as the corresponding index of the placement netlist,which shows that the decision consistency of the two stages is high.At the same time,the effective period of the meter is optimized by 15 ps,and the effective frequency is increased from 2.55 GHz to 2.65 GHz,an increase of 4%.Finally,the optimization problem of critical path is studied.According to the "global first,then local" critical path processing idea,the global and local critical path optimization strategies are formulated respectively.In the first step,according to the "parallel distribution" of a large number of critical paths in this CPU design,the TNS optimization pattern is chosen.The experimental results show that this mode can get a better WNS index,and the effective frequency is increased to 2.74 GHz,which is higher than the default mode of 2.65 GHz.In the second step,the local critical path which can not be optimized is analyzed,and the influence factors of path delay are Quantitative analysis.It is found that the starting trigger can be restricted to large size cells by adding constraints on adjacent non-critical paths,which reduces the total effort of critical paths and gets a smaller logic depth,thus reducing the delay of critical paths.Finally,a complete algorithm to determine the optimal constraint value is proposed.The experimental results show that the WNS index of the integrated network table is improved by 18%,the WNS index of the cell table is increased by 17.5%,and the effective period is increased from 2.74 GHz to2.79 GHz,the goal of timing convergence to 2.8 GHz is basically achieved.