Research On Ultra-Low Power PVT Tolerant Circuits Design Techniques

With the rapid growth of applications such as Internet of Things(IoT)or plantable medical electronics,the demand of low-power circuits arises.Thus the research on low-power and ultra-low power circuit design gains wide attention.The process,voltage and temperature(PVT)variatons seriously affect the performance and energy consumption of the circuits in the sub-/near-threshold regime because of the exponential relationship between the device current and the operating voltage.How to supress the PVT variations and improve the reliability of the circuits become a key problem for ultra-low voltage circuits design.In this thesis we first survey and analyze the impact of PVT variations on digital integrated circuits for ultra-low power applications.We study on the ultra-low power PVT variations tolerant circuit design techniques,which include the novel latch based PVT variations tolerant technique,the novel latch based error detection and correction(EDAC)PVT variations tolerant technique,ultra-low voltage PVT variations tolerant customized logic cells and library design technique,and ultra-low voltage PVT variations tolerant complex circuits design technique.Based on the research work,in this thesis we propose a wide-pulsed-latch based ultra-low voltage circuit design technique.And we build a two-phase latch-based and pulsed-latch based EDAC design method.Furthurmore,we develop a highly reliable ultra-low voltage logic cell library.Finally,we design a wide-pulsed-latch based ultra-low voltage 8-bit 8-tap FIR chip,an ultra-low voltage 8-bit 8051 microprocessor chip and an ultra-low voltage 16 Kb SRAM chip.The 65 nm CMOS technology based FIR chip measurement shows that the proposed FIR core achieves 45.2% throughput(frequency),11% energy efficiency(Energy/cycle),and 38% energy-delay-product(EDP)improvements over the flip-flop-pipelined baseline.Analysis results on a benchmark 6-stage pipeline in a 65 nm CMOS show that our proposed techniques can reduce the total area by 26-33%,the error detecting register count by 2.9-4.3 times and timing error rate by 5.5-37 times compared to conventional EDAC techniques.The measurement results of the 8-bit 8051 microprocessor chip in a 130 nm CMOS technology show it is fully functional from 1.2V down to 0.28 V.The power consumption of our microprocessor is 1.07-4.3 times less than previous works.The 16 Kb SRAM chip fabricated in a 130 nm CMOS is fully functional from 1.2V down to 0.33 V.The proposed SRAM has 1.5 times and 4.2 times less total power and leakage power than other works.Multi-chip measurements show the reliable and robust operation of our design techniques across PVT variations in the sub-threshold region.The results also show the high performance,high energy efficiency,ultra-low power and PVT variation tolerance of our proposed techniques.Thus the proposed techniques have very important theoretical value and practical meaning to research and also provide a promising solution for the ultra-low power applications.