Design And Implementation Of SSD Controller Based On PCIE Interface And Combination Of Calculation And Memory

The explosive growth of data in the era of big data puts higher requirement on storage technologies and storage devices.With its various advantages,SSDs with flash memory as storage medium are increasingly replacing traditional hard disk drives,the shrinking of the semiconductor and the increasing of the storage density have resulted in an raw error rate of 10^-3 order of magnitude for data in flash memory particles,the performance of hard disks is increasingly becoming a weakness of computer systems;SSD controller requires stronger error-correction capability and higher throughput to solve these problems.This paper addresses the application requirements of SSDs and completes the design of the key modules with the implementation of the circuit system in SSD controller.The paper starts with the requirements of SSDs and studies the use of the hierarchical design method in the PCIe bus protocol for data transmission.Based on the modular design method,the design of the DMA subsystem with PCIe3.0 high-speed interface has been completed,and the high-speed data transmission has been flexibly implemented.The codec circuit architectures are designed based on H matrix corresponding to LDPC codes.An adaptive modified minimum sum algorithm is implemented for the decoder and it performs a judgment and check operation while taking a row of sub-matrix operations which improves the throughput of the LDPC decoder.The design of the instruction set based on the check matrix H makes the codec dynamically configurable while single codec module's throughputs reach 4.8 Gb/s and 2.5 Gb/s respectively.The test platform for the codec system is set up to perform hardware simulation on the BSC channel that simulates flash memory in SSDs and 10^-10 order of magnitude BER data is measured which shows that LDPC codes show good error-correction performance in SSDs.In the paper,we innovatively propose the introduction of the calculation engine in the SSD controller.And the corresponding circuit is designed in the calculation engine for different application scenarios with completing the search algorithms for unstructured data.Sequential scan algorithm and hash inversion index algorithm are implemented which significantly reduces hard disk I/O load and improves equivalent transmission rate.Comparing the calculation engine's time for searching English documents with the time spent on the PC,the effectiveness of the calculation engine in SSDs is verified to some extent.Finally,a hardware system test platform is set up based on Xilinx's VC709development board while the corresponding firmware program and test program are designed to test system functions and the rate for reading and writing.While using a 4-channel PCIe 3.0 interface to transfer data,the maximum read and write rate is about 2.9GB/s,which is up to 72.5% of the theoretical limit speed and meets the rate requirement of industrial applications such as Intel.