Research On Parallel Processing Technology Of PCIe Bus Transaction Based On Tag

PCI-Express has a lot of technical advantages due to the packet-based protocol.All Non-Posted Requests require Completion.If multiple Non-Posted Request transactions is outstanding,the returning CplDs are permitted to pass each other.Tag filed could provide these transaction unique ID and a solution of Completion buffer distribution and disorder.Memory Read Transaction concurrency,Transaction fragment and the size of CplD buffer are related to Tag nanagment mechanism.There no clear instruction and reference design about how to convert the backend data request to the corresponding PCIe TLP.The management and semantic extension of Tag,CplD ordering based on tag have been widely researched.In this paper,the PCIe transaction concurrency techniques based on Tag has been researched,and some optimized scheme is proposed.This paper mainly studied the following content:1.Current research about PCIe transaction transmission based on Tag and Hard IP core Interface solution has been studied.The mechanism of PCIe transaction Dynamic Granularity Concurrency base on Tag(T-DGC)has been proposed.Provide a solution about the problem of buffer resources increasing excessively with improving concurrency and bandwidth utilization and CplD disorder.Complete the design of the core architecture of the PCIe core interface.Data read efficiency,buffer ram resource usage and resource utilization modeling and analysis.2.Module division of the core architecture implementation scheme.Complete the CplD buffer allocation,Memory Read Transaction concurrency and the CplD ordering.And then complete the design an implementation of PCIe IP core interface logic.3.Verification strategy of T-DGC model has been studied and verification platform has been designed.The whole design comprehensive verification has been done to ensure that the design code complete all functions defined by the optimization architecture correctly.In conclusion,this paper presents The T-DGC in order to solve the problem of buffer resources increasing excessively with improving concurrency and bandwidth utilization.Because this T-DGC model can dynamically control the concurrency granularity according to data requests and solve the problem of CplD disorder,the design for high-performance PCIe bus has a reference value and practical value...