Hierarchical approach to semiconductor yield modeling: Applications of generalized linear models

In this research we propose a hierarchical modeling approach to model semiconductor end-of-line yield based on measurements collected in the manufacturing process. Semiconductor manufacturing is well-known for its complexity and the enormous amounts of data generated during the manufacturing process. Combining these with a complicated sampling strategy within each process, a one-stage modeling can be very difficult. By introducing intermediate variables, a two-stage modeling technique can facilitate the analysis of this problem. The first stage modeling is called "meta-modeling", which is used to identify the key intermediate variables critical to the yield. The second stage modeling is called "sub-process modeling", which is used to establish the relationship between intermediate variables and their key sub-processes. This approach allows us to analyze the relationship between intermediate variables and all key sub-processes independently, and then combine all effects to predict wafer yield by some of these key sub-processes. Generalized linear models are used for sub-process and meta-modeling due to their ability to tackle categorical and integer responses. This research uses hierarchical modeling to predict yield by using Poisson and multinomial logistic regression. Several modeling issues are addressed.