Research On The Design Of Low Power Domino Circuit In Nanometer CMOS Technologies

As the rapid development of the IC technology, the speed and integration of the chip increase greatly. This makes the power density of the chip increase dramatically. However, in order to prolong the battery life of the mobile device and decrease the cost of heat radiation and package, the power consumption of the chip should be reduced as more as possible. So, power consumption is an important issue that should be considered in the chip design. Due to the superior speed and area characteristics, domino circuits have been extensively applied in critical path of high performance ICs. Thus, power consumption is one of focuses during the CMOS domino circuits design.First, the background knowledge of low power circuits design is introduced, which includes the makeup of the power dissipation and some regular low power design techniques. And the characteristics and principle of domino circuits are analyzed. Then, according to the characteristics of power for domino circuits, two new domino techniques are proposed. The first one is based on floating-gate controlling threshold technique, after introducing the work theory, characteristics and the SPICE model for floating-gate MOS, floating-gate controlling threshold technique and the characteristics of it’s leakage power is analyzed and simulated.On these basis.the floating-gate controlling threshold domino circuits are porposed.The second one is a new voltage scaling technique, we introduced it’s work theory and characteristics, then compared the power dissipation of some normal domino circuits with different techniques.According to the simulation by HSPICE, we can see that both of the two new domino techniques can reduce the power dissipation effectively.