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Fpga-based Radar Digital Signal Receiving And Processing

Posted on:2013-04-02Degree:MasterType:Thesis
Country:ChinaCandidate:Y XuFull Text:PDF
GTID:2248330371470660Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
With the development of ultra-high-speed digital processing circuitry and software radio thinking, software, radar has become the main development direction of modern radar. Software radar system, the digital radar receiver is one of the most important technology. In the context of increasingly high conversion rate of today’s high-speed A/D conversion circuit, radar, digital receiver processing rate of the digital signal processor, a higher demand. Traditional general-purpose DSP due to its limited processing speed are often unable to deal directly with the high-speed data stream generated by the A/D chip sampling of the IF signal, and the use of FPGA-effective solutions to the above questions.In this paper, the FPGA-based radar intermediate frequency digital signal acquisition receiver and detection processing design. Depth analysis of the non-phase parameters pulse radar’s intermediate frequency signal characteristics, the focus against radar IF signal digital receiver method and detection processing method in an FPGA, VHDL language description, schematic design, resource call, etc. means one by one to achieve a each algorithm module, combined with the large number of theoretical analysis and software simulation, carried out a thorough verification of the proposed design.Radar IF signal, digital reception part of the focus on the IF signal to match the receiver and digital down-conversion processing, and discuss the basic structure of the digital radar receiver, the IF signal sampling rate selection method, the matched filter principle and structure of digital down conversion andimplementation, analysis of the spectrum function of the radar IF signal estimation method, pointing out that the digital down-conversion contains a digital oscillating controller, digital mixer, digital filtering, extraction, and other sub-modules, and finally each child match the filter and digital down-conversion modulealgorithm implemented in the FPGA, and simulation software Matlab/ISE/modelsim, each algorithm.Signal detection processing section focuses on the CFAR processing, video integration testing and the same frequency interference suppression and signal detection approach, CFAR in conditions of constant false alarm rate to reduce background noise interference and improve signal detection probability;video integration testing can effectively improve the signal to noise ratio of the echo signal to improve the receiver sensitivity, enhanced small target detection capability of the echo echo signal in the same frequency interference can further filter on the basis of the above processing; same frequency interference suppressioncomponents, effectively reducing the probability of false alarm.
Keywords/Search Tags:IF, digital down conversion, filter, target derection, FPGA
PDF Full Text Request
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