Matrix Code And LDPC Research And Design For Memory Hardened

With the development of integrated circuits(ICs),the size of ICs has become smaller,making the supply voltage smaller,resulting in circuits more susceptible to noise,and circuits becoming more susceptible to failure.Therefore,it is a significant research topic to ensure ICs are protected against radiation in the special environment such as the cosmic environment or nuclear radiation.Memories are important part of ICs,and the increase in unit density increases the probability that multiple errors occur in the memory.In this paper,the matrix code error correction circuits are designed to reinforce the SRAM,which can correct the multi-bit flipping of the memory by the high-energy particles in the radiation environment.A word is logically divided into multiple 4th order matrices,and a rectangular cycle parity method is proposed to construct the check bits in encoding design.The designed matrix error correcting code can correct the errors of the 6-bit data width in a word with a data bit width of 16 bits.The layout of the data bits is arranged to prevent the error correction code circuits failure when the redundant bit flip.To reduce the decoding algorithm complexity,the redundant bits were extra added and the error correction capability was reduced.Compared to currently known error correcting codes,various decoding schemes are designed to have a better mean time to failure(MTTF).This paper also designed an EG-LDPC majority logic decoding circuit for enhancing NAND Flash memory.In the circuit implementation,firstly,H submatrix storing of the EGLDPC is replaced by storing the position of ‘1' in the submatrix;then,the information circulant matrix is used instead of the loop of the submatrix component vector,and the vector of data circulant matrix is read and computed through the position of ‘1' in the H submatrix.Since the information is converted into a circulant matrix,each call of the data in the matrix means that all the data are simultaneously verified.Therefore,when all the positions of ‘1' in the H submatrix are called for the data cyclic matrix,the codeword decoding is completed.Finally,the designed circuit is functionally simulated to ensure the correctness of the circuit.EGLDPC is majority logic decodable code.In the traditional majority logic decoding,for the codeword with the code length n,n decoding cycles are needed to complete the decoding.The proposed decoding circuit can decode all the bits of the codeword in one decoding cycle.The calculation results show that the proposed decoder greatly reduces the storage resource occupation and increases the circuit reliability in radiation environment in the case of the same throughput rate than traditional decoder.