Design And Implementation Of RF Transceiver Low Phase Noise PLL

With the country in recent years, efforts to support intellectual property rights strengthened.Not only bring vitality to the electronic communications sector, but also led to the development of IC design industry. Frequency Synthesizer as the core circuit of RF transceiver chip design, the development of electronic communications industry to develop a frequency synthesizer provides a good opportunity for development, the high-frequency,low-power, low phase noise frequency synthesizer direction become the focus direction for researchers, but also as the core technology product performance core competitiveness.PLL frequency synthesizer using signals of different frequencies output loop feedback principle to supply chips to other modules such as a clock mixers, and digital circuits. The design of the main goal is to achieve a low energy output 1.8 GHz frequency and the phase noise is applied to the wireless communication RF transceiver frequency synthesizer.The main application of this article locked loop designed in RF transceiver. The analysis is complete and the influence of the phase noise generated according to indexes devised a relatively low phase noise PLL system. Specific action by the phase locked loop set forth in the RF transceiver play of this article to introduce the actual operating mode PLL specific circuit structure and lock, and then introduced a frequency synthesizer system PFD, the specific structure of each part of the circuit CP, LPF, VCO, Divider, AFC, etc.,simulation methods and ways of working. Finally, focus on research phase noise frequency synthesizer system produced several models, as well as the phase of each sub-circuit noise generation and conduction mechanism, establish a loop to achieve low phase noise PLL phase noise of the system can be suppressed circuit structure.The main focus of the paper is to study the impact of various circuit sub-module of the phase noise. First, the noise in the loop oscillator lies primarily tail current source and the differential pair flicker noise tube, through the analysis using a unique bias circuit to reduce the flicker noise of the tail current source is also suppressed differential pair of flicker noise. Next, effect of non-ideal factors for CP circuit loop is proposed low voltage mismatch high linearity deadband small CP circuit. For the control circuit uses digital control to achieve the effect of different bit width modulation phase noise, modulation of digital control technology will move from the center frequency of noise about the high frequency. Following the adoption of the LPF filtering effect, so that the noise generated approximately no effect on the control voltage.At the same time the automatic frequency control(AFC) loop to achieve control of the VCO gain correction to obtain a nearly constant gain to suppress the phase noise loop transfer.By analyzing the theory with the actual chip engineering technology, SMIC 0.18?m CMOS technology can be applied to achieve online radio transceiver system PLL subsystem. The output frequency at 1.8 GHz, the center frequency of offset phase noise at100 k Hz and 1MHz is-99.29 d Bc / Hz and-122.50 d Bc / Hz.