Research On Continuous Time Sigma-Delta Modulator Modeling And Circuit

With the development of communication system, the bandwidth of the next generation wireless communication system needs to reach tens and even hundren MHz, and the dynamic performance needs to be same. The ADC needs wide bandwidth, low power, and high resolution. As the hot issue of this field, the Sigma-Delta ADC has advantages of lower power consumption and higher conversion accuracy compared with the traditional Nyquist ADC. Since the continuous time Sigma-Delta ADC has the natural ability of inherent anti aliasing filter and the less restriction of bandwidth of opamp without serious set-up process, it can work under lower power and lower voltage in the field of high speed convert.The research is baesd on the Sigma-Delta modulator which is the key module of continuous time Sigma-Delta ADC. Firstly, the STF characteristics between feedback and feedforward modulator are analyzed. Combined their advantages, we propose a hybird Sigma-Delta modulator. Secondly, exploiting the SD toolbox of matlab, the transfer function H(s) of the continuous time Sigma-Delta modulator is synthesized using impulse invariance. In order to reduce the power of the system, the second integrator was replaced by passive RC integrator, and zero-order feedback is advanced to the last integrator to cancle the adder. With the bandwidth of 10 MHz, the OSR equals to 16, the SNDR is 68.6 d B, SFDR is 100.9 d B and ENOB is 9.5 bits. The noideal factors including finite GBW, mismatch of feedback DAC, variation of loop filter coefficients, clock jitter, loop delay and comparator offset are analyzed. The evaluation of the noideal factors on system are modeled mathematically. The capacitor tuning array calibrates RC variation, and NRZ pulse degrades the impact of jitter, and the zero-order feedback absords loop delay, and DWA cancles DAC mismatch.Based on SMIC 0.18?m CMOS process, we designed circuits from a stable three-order continuous time Sigma-Delta modulator which has been verified. The SFDR is 98.4 d B, SNR is 81.1 d B, and ENOB is 11.2 bits by 320 MHz sample rate, 16 OSR and supply voltage is 1.8 V.