.14 ​​bit, 128mhz Continuous-time Low-power Sigma-delta Modulator And Design,

The fast development in the wireless telecommunication makes the high performance analog-to-digital converters great roles in different kinds of receivers, for they are the connection between the analog and digital world. The oversampled ADC has some advantages over Nyquist ones when the signal bandwidth is lower than 20MHz and the resolution is relatively high, i.e., higher than 12bit. The continuous-time sigma delta ADC has become a hot research direction for its potential in low power consumption over discrete-time counterparts. This thesis focuses on a 14bit resolution,1MHz signal bandwidth continuous-time sigma delta modulator. It finished the research on the techniques of continuous-time architecture and the design of the circuits. The prototype was taped out and tested successfully.The thesis makes use of some special techniques to overcome the drawbacks of continuous-timeΣΔmodulator which are analyzed in detail. The whole system is a 5th order,3-bitΣΔmodulator. The excess loop delay has been improved by adding an extra DAC around the quantizer with modifying the relative loop transfer function. Multi-bit DAC is used to reduce the sensitivity of clock jitter to the system. Meanwhile, the timing of the system is as easy as possible so that the clock generator can be simple to reduce the jitter source. The RC variation due to process and temperature is compensated by the 3-bit off-chip tuning code which can tunes the C-array, thus guarantees the stability of the system. In order to meet the low power requirement, the feedforward architecture and active-passive hybrid loop filter are chosen. Moreover, the power-hungry summing block before the quantizer is omitted. The summing function is performed by the fifth integrator through the discrete-time differentiation. In order to improve the linearity of the multi-bit DAC, the DWA algorithm is adopted.The prototype was taped out in 0.18um CMOS process. The test result shows that 84dB dynamic range,79.5dB SNR and 78dB SNDR are achieved. The power consumption is only 9mW and FOM reaches 0.58pJ/conv. The core area is only 0.43mm2. In the process of testing, the tonal behavior of traditional DWA algorithm was discovered and some further research on this problem was made then.