Higher Order Continuous Time-based Sigma-delta Modulator Research And Design

In recent years, more attention are payed to Sigma-Delta Modulator, due to its advantages such as high-precision, high-integration and low-power. Besides, along with the development of novel techniques, such as cascaded structure, multi-bit quantizer and dynamic calibration, the performance of wide-band Sigma-Delta ADC has been improved a lot. Therefore, it is possible to apply Sigma-Delta ADC for wide-band applications. However most of Sigma-Delta ADCs with signal band up to MHz employ switched capacitors in the past. Because there are mature design methodologies and robust system structures. Compared to DT (Discrete Time) Sigma-Delta ADC, CT (Continuous Time) Sigma-Delta ADC has the advantages of low-power and inherent anti-aliasing characteristic. These features can probably increase the life of battery and reduce the system complexity, which are essential for portable wireless equipments. ADC modules are necessary for Digital TV, and communication systems. A CT Sigma-Delta ADC can satisfy these requirements well.In this paper A CT Sigma-Delta Modulator is designed for the application of video decode chip, with 4MHz signal bandwidth. The sampling clock frequency is limited by the clock of the whole system, therefore the OSR (OverSampling Ratio) is equal to 8. It is difficult to obtain a high performance Sigma-Delta ADC with such a low OSR. As a result, fifth-order feedforward structure and 10-level quantizer are used in this modulator. To shorten the desigh circle, a Matlab module of the whole system is built and 72.2dB SNDR is obtained. The modulator employs summation ahead technology so that a summation circuit is omitted and the power consumption is reduced. Detail nonideal analysises are conducted and modeled. Additional transfer function, lool-up table structure, extra white noise are added to the whole module to get the detail design guideline. During the circuit design, noise analysis on the main noise part—front-end circuits are given. Design considerations of key circuits in terms of mismatch, delay, power and so on are analyzed. The SNDR of the whole system is 68.9dB in the typical corner and above 65dB in every corner. As the whole system employs fully differential structure, the symmetry of the layout is seriously considered, including RC net, operational amplifier, quantizer and feedback DAC. What's more, special layout method is used for DAC module, because its mismatch error is fatal to the performance of the whole system. The post-layout SNDR of the whole system is 60.9dB, under a 3V,2MHz sinoder input signal and 64MHz clock.