| Low-power and wideband analog-to-digital converter has been one of the research focuses recently in wireless communication. Compared to discrete-time sigma delta modulator, continuous-time sigma delta modulator has a wider input bandwidth and inherent anti-aliasing feature, which relaxes the requirements of prefilter in analog-to-digital converter and thereby reduces the overall system cost.Multibit CT Sigma Delta modulators are often implemented using the feedforward topology which typically causes an undesirable out-of-band peaking in STF. Due to the presence of strong out-of-band blockers in wireless applications, any peaking in STF translates into a reduction in system performance. Based on the signal bandwidth and anti-aliasing requirements for wireless communication, this paper studies a continuous-time sigma delta modulator with peaking-free STF,10MHz signal bandwidth and12bit resolution by analyzing and improving the architectures of modulators. The modulator based on the peaking-free STF methodology is implemented with a proposed fourth-order feedforward-feedback mixed architecture. Firstly, the noise transfer function is obtained by matlab to satisfy the requirement of the modulator. And coefficients of the loop filter in the new system architecture are computed to model the system in simulink. Then the basic spectations of each module are determined by optimizing coefficients of the loop filter and simulating the effects of the nonidealities, such as finite gain-bandwidth product, time constant error and clock jitter. And more detailed circuit parameters, such as resistors of integrators and feedback currents, are obtained by Verilog-A modeling in spectre. Finally, the system blocks including integrators, quantizer, latch, feedback DAC and clock generator are designed.The modulator is realized by SMIC0.18um CMOS Mixed Signal process. The core achieves81dB SNDR under320MHz sampling frequency while consuming37.2mW from a1.8V supply and provides a peaking-free STF. |
PDF Full Text Request