Research And Design Of High Speed Broadband Continuous-Time Sigma Delta Modulator

Sigma Delta modulators make the design of high resolution Analog-to-Digital Converter (ADC) feasible by employing the oversampling technology combined with quantization noise shaping methodology. The design of Discrete-Time (DT) Sigma Delta modulator becomes more and more difficult when regarding the fields that high requirements of signal bandwidth are needed, such as wireless communication. However, the Continuous-Time (CT) architectures decrease the demands of block specifications and are widely used in the realizations of low power Mega Hz signal bandwidth ADC.The basic principles of Sigma Delta modulator are introduced in this design firstly, focusing on the analysis of the difference between DT and CT Sigma Delta filters; for the high speed ADC design in Mega Hz signal bandwidth, the system level design and analysis are completed, also the implementation of circuit level design. At the system level design, the main work includes: Based on the theoretical analysis, a three-order single-bit CT Sigma Delta architecture is adopted and modeled in discrete domain, including the design and optimization of the Noise-Transfer-Function (NTF), modeling and simulate in Simulink; then, the loop function is converted to continuous domain by using the theory of Impulse-Invariant-Transform (IIT), and the Digital-to-Analog Converter (DAC) nonidealities introduced by the transformation are illustrated; the specifications of each blocks are defined thanks to the discuss of the loop filter nonidealities. In the circuit implementation, the low-voltage cascade bias circuit, gain-boosting technology and CT common-mode feedback (CMFB) are presented in the amplifier design of the modulator to realize low power consumption and wide bandwidth; meanwhile, extra positive feedback is introduced in the comparator circuit, which increases the speed of comparison, decreases the power consumption at the same time; finally, the simulation results and analysis are put forward, which show that the requirements are met well, and then the layout design and verification are carried out.The implementation is designed in SMIC 0.18μm CMOS process, the module circuits and the top modulator are simulated and analyzed under the Cadence environment. The simulation result of post-layout shows that 68.7 dB and 68.6 dB signal-to-noise ratio (SNR), 11.13 bits and 11.11 bits of effective number of bits (ENOB) are achieved respectively, with the input signal frequency of 500 KHz and 1.5 MHz, when the amplitude is 0.5 V. Consuming only 1.8 mW, the proposed Sigma Delta modulator reaches a high level in the field of Mega Hz signal bandwidth.