Design And Implementation Of Digital Down Converter

Software radio is an innovation form of wireless communication, and will promote the continuous innovation in the field of wireless communication. With the rapid development of software radio, it is widely used in the field of military and civil communication and other fields. In software radio system, digital down-conversion(DDC) technology is one of the key technologies, which has gradually become the focus of research. FPGA is a configurable logic circuit. The characters of FPGA include programmable, high flexibility and integration. Based on FPGA, the implementation of DDC conforms to the flexibility and openness requirements of the software radio. This paper considers the performance and cost issues in FPGA design and adopts the cascade method. According to the algorithm principle of DDC and the algorithm characteristics of each stage, this paper designs the efficient implementation structures of DDC. The main research contents of this article are as follows:According to the theory and the function of DDC, this paper designs DDC at the register transfer level(RTL) and completes the functional verification and logic synthesis. Firstly, this paper describes the theory of multi-rate signal processing, CORDIC algorithm, DA algorithm and special filter. Then, according to the functions of DDC, the system is divided into two big modules, including the down-conversion module and the decimation filter bank module. Secondly, the down-conversion module is designed with parallel pipeline structure, on the basis of CORDIC algorithm. It can produce the sine and cosine signal and complete the multiplication simultaneously which are the functions of NCO and mixer. Therefore, this structure has high data throughput, and saves the lookup table and two parallel multipliers. Finally, based on the theory of extraction and the poly-phase decomposition technique, this paper designs the decimation filter bank module, which is divided into CIC decimation filter module, CIC compensation filter module, HB filter module and FIR filter module. In the design of CIC decimation filter module, according to the principle of translocation transformation and Nobel identical equation, the extractor lies between integrator part and comb filter part. The comb filter part operates at lower clock rate, and the number of delay unit is reduced significantly. Using the symmetry of filter coefficient, CIC compensation filter module is implemented with the structure of DA algorithm combining with extraction, and HB filter module is implemented with thestructure of DA algorithm combining with multiphase. These two kinds of structure extract data firstly, and then conduct the filtering operation. This can avoid the unnecessary operation, thus improving the operation efficiency effectively. FIR filter module adopts the serial-parallel DA algorithm structure, which saves considerable hardware resources and improves the speed of system operation.This paper verifies the function of the design through MATLAB and Modelsim. The calculation accuracy of CORDIC module in the down-conversion module is up to 10-5 orders of magnitude. Compared the results of Modelsim with that of MATLAB, the relative error value is up to 10-5 orders of magnitude. This precision meets the design requirements. Under the standard process library of SMIC 65 nm, the design of DDC is synthesized with Design Complier tool of Synopsys corporate. The max clock frequency of the DDC is up to 290.698 MHz and the comprehensive area is 99496.800420?m2. The design has good portability and can be upgraded and extended the function easily. There is a certain reference value for research.