Design And Implementation Of Fir Filter Based On FPGA

FIR filters are widely used in digital signal processing because of their strong stability,strict linear phase and easy hardware implementation.At present,there are classic filters with fixed coefficients and modern filters with variable coefficients.The classical FIR filter is applied when the frequency distribution of the unfiltered signal is known,and its coefficients are determined according to the performance.Under certain conditions,the modern filter can estimate the target signal by using the statistical characteristics of the unfiltered signal and noise,and its coefficients are adjusted by adaptive algorithm.This article optimizes the FIR filter in two aspects,one is the structural optimization of the classical FIR filter from the hardware realization level,and the other is to propose a variable step size algorithm with lower hardware implementation complexity in the algorithm level.The higher taps filters has,the better performance filters do,However,a large number of look-up table resources are needed to implement the filter in distributed architecture.A new distributed arithmetic architecture based on symmetric look-up tables is proposed in this paper,for solving the problem of high-order linear FIR filters using too many look-up tables.Based on the symmetrical characteristics of linear filter coefficients,the segmented look-up table is improved,and a smaller depth look-up table is designed,which solves the problem of data being repeatedly stored,so that the depth of look-up table can be reduced by nearly half,and the working frequency of FIR filter is improved by time division multiplexing technology and pipeline technology.Synthesis of a 1024-tap FIR filter based on proposed architecture is done on Xilinx XC5VLX110 T FPGA chip.Compared with the segmented look-up table architecture,the proposed one saves 48% block ROM resources and increases the operating speed by 15%.Finally,the filter used symmetric look-up table structure is implemented on the experimental platform.The experimental results show that the filter based on symmetric look-up table works well.Among the existing adaptive algorithms,variable step size LMS algorithm appears in many adaptive filters because of its low complexity and good convergence effect.However,most of these algorithms have exponential operation,square root operation or division operation,which also brings difficulties for hardware circuits to implement these algorithms.This paper choose Sine function to limit the change process of the step size factor with the error signal,the Sin-LMS algorithm is proposed and the convergence effect of several variable step size algorithms is drawn in the same MATLAB model.The comparison results show that,compared with the other four algorithms,the proposed new algorithm has faster convergence speed and lower misalignment error.When using hardware to implement sin LMS algorithm,the CORDIC algorithm can only use the shifter and the adder to calculate the sin function value,which reduces the hardware implementation complexity of the Sin-LMS algorithm.Then the saturation and round method is used in fixed-point operation to reduce finite word length effect.After the design of all the modules of the adaptive filter,the adaptive interference canceller based on Sin-LMS algorithm is completed on the experimental platform.Two signal generators are used to generate the desired signal and noise signal.The adaptive filter is observed through the oscilloscope.The experimental results show that the filter works well.