Research Of Digital Down Converter And Matched Filter Based On FPGA

Nowadays with the fast development of Mobile Communication,4G technology has been proven, and it is put into use gradually. However there are some problems about compatibility between GSM,3G and4G and how to transform smoothly from3G to4G even5G, while Soft Defined Radio (SDR) can be a good choice to solve the problems. This paper has a good research of Digital Down Converter(DDC) and Matched filter which is the key technology of SDR receiver.Firstly, the whole process of Digital Down Converter design is researched, which includes characters choose, structure design of DDC, Low Pass Filter(LPF) design and simulation of Digital Band Pass Transmission System. The key research contents are show as follows:Firstly, design and optimization of multi stage DDC is presented, which has a good advantage of computation complexity and performance compared with the single stage DDC, Secondly, the structure of single channel and multi channels DDC is built and compared, Finally, Digital Up Converter(DUC) structure is designed and module of Soft Defined Radio transmitter is also built. Meanwhile, Single channel and multi channels pass band transmission system constituted of QPSK signal, DUC and DDC is simulated.Secondly, improved matched filter used in DDC is introduced in this paper by two ways. The first one is try to design matched filter directly. Matched LPF, Square Root Raised Cosine(SRRC) filter and Square Root(SR) Nyquist filter which is based Remez algorithm by simply iteration is analyzed and compared in this paper. The Inter Symbol Interference (ISI), transition and passband ripple are found to have a large influence on the Bit Error Rate(BER) of DDC. The other is to design Nyquist filter firstly and then use spectrun factorization method and iteration to obtain optimal two SR Nyquist filters. What is more, this paper presents a new method to design a novel SR Nyquist filter, which bases on linear programming Nyquist filter design. This method will get better stopband attenuation and flexibility at the cost of losing ISI which will be determined by a value. At same time, Peak to Average Ratio(PAR) restraint is also designed, its performance optimization after quantification is studyed which is useful to application.At last, this paper uses FPGA to realize DDC. By making input and output of each module both in Matlab and FPGA as well, the simuluation of FPGA is mapped to Matlab, so that the strong function of date calculation and data analysis of Matlab can be fully used. Then a comparision of BER between fixed point DDC simulation and floating point DDC simulation by Matlab will be presented.