Modeling And Simulation Of Thermal Stress Induced By Tapered TSV

In three-dimensional integration,through silicon Via?TSV?is an important structure to achieve vertical interconnection.However,TSV technology still has many chanllenges,how to quickly establish its equivalent model and to extract its distribution of thermal stress with accurate is one of them.A common way is to simplify it as a cylinder and analysis it with transmission line theory.However,the inclination might be as large as 20degree in real TSV due to fabrication limitation,thus modeling and analysis on tapered TSV turns out to be very necessary.The thermal stress of tapered TSV produced by the thermal expansion coefficient mismatch between the annealing temperature of 275 degree and the room temperature of25 degree was studied by Comsol and Matlab software in this thesis,and the effect of thermal stress on device placement was obtained.The main works of this paper can be summarized as follows:The TSV structure and the thermal stress generation mechanism of the three-dimensional interconnection were studied.Based on the above,the single tapered TSV model was selected firstly.The model was established,the thermal load was applied,the thermal stress was analyzed and the results were compared with the cylindrical TSV with the same upper surface radius.The thermal stress values in the tapered structure were larger and the distribution was more uniform.The formula for calculating the plane stress and mobility in two dimensions was given.By calculation we can see,the increase of the radius of Cu cone leads to the increase of stress and keep out zone?KOZ?size.The increase of the thickness of the SiO₂ layer makes the effect of stress buffer layer more effectively,the maximum surface stress and the KOZ size decrease,but the effect is weak.The increase in cone angle results in a decrease in stress and KOZ size.Considering the existence of numerous TSVs in each layer,the TSV array structure composed of four tapered TSVs is proposed,the factors that affect the thermal stress of the tapered TSV array are array spacing and arrangement.In the case of arrays,the stress distributions of the single tapered TSV are superimposed on each other,making it difficult to draw conclusions through the mean and the maximum surface stress,so the comparison of KOZ size is the most important.As the array spacing of Lattice-type arrangement increases,the KOZ size of a single TSV decreases,the overall KOZ size increases and the KOZ region is connected.Compared with lattice-type arrangement,the rhombic arrangement increases the KOZ size of a single TSV,reduces the overall KOZ size and makes the KOZ region independent of each TSV because of the offset effect.Considering the existence of multi-layer TSV in practical applications,a double-layer TSV structure consisting of intermediate metal interconnections is proposed.The distribution of thermal stress at each height is as follows:In terms of surface mean stress,the double-layer structure shows a low distribution between the two ends,which is similar to a single tapered TSV.In the metal interconnection layer,the average stress decreases first and then rises.In terms of surface maximum stress,the maximum value appears on the upper and lower surfaces of the metal interconnection,forming a bimodal distribution curve.The influencing factors are analyzed as follows:The increase of the radius of Cu cone can increasing not only the maximum stress but also the influence area of stress.The increase in the thickness of the SiO₂ layer reduces the maximum stress in TSV and has a slight effect on the placement of the device.The increase of the cone angle leads to the increase of the stress,but the device placement would not be influenced by the increasing cone angle due to the metal interconnect structure.