Study On The Effect Of Through Silicon Via Induced Stress On Adjacent MOS Devices

In recent years, three-Dimensional Integration(3D IC) has received extensive research and attention owing to its good performance and application prospect. 3D IC based on the through silicon via(TSV) has significant advantages in function, size and delay, which is the main implementation techniques in 3D IC currently. But due to mismatch in the coefficients of thermal expansion(CTE) of silicon and via, stress in surrounding silicon is induced near TSV interconnects in 3D IC. According to the piezoresistive effect theory and deformation potential theory, the induced stress can change the mobility and energy band of substrate material, which have a significant influence on the saturation current and threshold voltage of MOS devices near TSV. Furthermore, the variation of MOS devices performance can interfere the circuit characteristics, and even affect the system performance.In this paper, an analytical model for a single TSV induced stress distribution is developed firstly. A mobility variance model is then obtained combining with piezoresistive effect theory. The impact of induced stress on MOS devices are also analyzed. At last, the arrangement of MOS devices near TSV are optimized based on the Keep-Out Zone(KOZ) of induced stress. The paper’s major conclusions are outlined as follows:1. An analytical model for TSV induced stress distribution near substrate surface has been developed. Firstly, an analytical model for substrate-Cu TSV induced stress distribution is developed based on 3D semi-analytical model with curve fitting method. The FEA simulation result show that the analytical model has a good accuracy. Secondly, The stress distribution on the wafer surface in the Cartesian coordinate system are presented to consider the stress effect in different locations.2. A mobility variance analytical model caused by TSV induced stress has been developed. Firstly, an analytical model for mobility variance caused by TSV induced stress is developed based on the piezoresistive effect theory with the induced stress distribution analytical model. Secondly, the impact of TSV diameter, distance, crystalorientation, carrier types, annealing temperature, and the difference of CTEs on mobility variance are discussed.3. The impact of induced stress on MOS devices have been studied. Firstly, the impact of induced stress on the saturation current of MOS devices are analyzed based on the mobility variance model with ISE-TCAD. Secondly, the impact of induced stress on the threshold voltage of MOS devices are analyzed based on deformation potential theory.4. The arrangement of MOS devices near TSV have been studied. Firstly, the KOZ of induced stress distribution is analyzed, and the optimization strategy for the area of KOZ is given. Secondly, the arrangement of MOS devices near TSV are optimized based on the KOZ.