| Compared with two-dimension integrated circuit limited by the increasing number of metal layers, the three-dimension integrated circuit technology, which takes advantage of vertical interconnect by stacking chips, has many benefits including shorter wire-length, lower power dissipation and heterogeneous integration. And through silicon via(TSV), the most effective way to realize vertical interconnect, may give rise to many unintentional challenges, especially the mechanical reliability problems. In addition, thermal stress induced by TSV can lead to the change of performance of devices. Therefore the impacts of TSV induced mechanical stress on carrier mobility, threshold voltage and saturation current of devices are mainly discussed in this article. And conclusions drawn in this paper are shown as follows:(1) Modeling the TSV induced thermal stress. According to the theory of Elastic Mechanics, a mathematical model of TSV thermal mechanical stress is built based on the plain strain and plain axisymmetric problems. Afterwards, the unknown coefficients should be solved through the boundary conditions gained by the concrete structure of TSV.(2) Verifying of the stress model through many kinds of TSV. it is necessary to study the verification of the model of TSV induced thermal stress making use of many types of TSV in this paper, namely conventional cylinder, newly presented annular TSV and coaxial TSV. Then a comparison between the data of mathematical model of TSV induced thermal stress and the results of finite element analysis should be made in a universal coordinate system. Subsequently, stress tensors in Cylindrical coordinate system can be converted to Cartesian coordinate system in order to use.(3) Analyzing the variations of carrier mobility under different channel direction. The effects of TSV thermal stress on mobility are given with channel direction along [100] and [110] crystal direction respectively. When the channel direction is set along [100] direction, the variations of electron mobility are more significant than those of hole. And electron mobility along coordinate axes have a greater change than the zone between Axes. But for the [110] channel direction, variations of hole mobility should not be neglected compared with electron mobility, especially for the hole in the zone between the coordinate axes.Based on the results of mobility variations, the appropriate placement style of devices can be achieved to keep the timing performance of chips.(4) Analyzing the variations of threshold voltage. TSV induced thermal stress can cause the shifts and splits of conduction band and valence band, which will bring about the degradation of threshold voltage. It is found that the threshold voltage of a NMOS device under TSV induced stress decrease by 32 m V, while 50 m V for the PMOS device.(5) Analyzing the variations of saturation current. As mentioned above, TSV thermal stress can change the carrier mobility and threshold voltage, which will result in the variations of saturation current on the basis of the theory of semiconductor devices. As for the NMOS device, TSV stress can cause the rise of the saturation current. And the variations of saturation current along X axis are more significant, while the variations along Y axis can be neglected due to the insignificant changes. But for the PMOS device, the saturation current along X axis increase, while decrease along the Y axis.(6) The impacts of physical parameters of TSV. The effects of the physical parameters of TSV on saturation current are also discussed in this paper. And it is found that the smaller TSV radius, thicker insulating layer and combination of W and Si O2 are beneficial for saturation current. |
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