Analysis And Simulation Of Thermal Stress In Through Silicon Via Based On Stress Buffer Structure

Through Silicon Via(TSV)technology,as the most effective method to achieve vertical interconnection in three-dimensional integrated circuits,has received extensive attention from researchers.However,the use of TSV has also introduced new problems,especially the thermal stress problem,which has a serious impact on the performance and reliability of the circuits.Therefore,the analysis and optimization of thermal stress are particularly important in the study of TSV.In this paper,a TSV structure based on stress buffer structure is presented,and its thermal stress distribution is analyzed.The simulation results show that compared with the annular TSV structure,the hoop stress is reduced to 144 MPa,the optimization reaches 51%.The radial stress is reduced to 134 MPa,and the optimization reaches 53%.The optimization effect is very obvious at the boundary of the through via.The influence of different parameters on thermal stress is studied.The simulation results show that the thermal stress and the area of Keep-Out Zone(KOZ)will reduce with the radius of filling silicon oxide or the thickness of buffer layer increasing,while the thermal stress and the area of KOZ increase with the radius of through hole increasing.Combining with the theory of thermal stress in elasticity,the thermal stress distribution formula of TSV is deduced.The influence of thermal stress on the mobility of electron and hole carriers in different directions is calculated,and the optimal placement of different types of transistors is obtained.At the same time,the thermal stress distribution of TSV array is discussed,and the influence of array spacing and array arrangement on thermal stress is analyzed.The KOZ sizes of different array structures are compared emphatically.The results show that as the spacing between arrays increases,there is connectivity in the inner KOZ region between adjacent TSVs while the outer KOZ region is no longer connected,and the overall KOZ area of the array increases.When the layout is adjusted to a diamond shape,the KOZ area of a single TSV increases.the thermal stress between adjacent TSVs cancels each other out.The overall KOZ area reduces,and there is no overlap.