Stress Engineering And Device Study On Sub 40nm CMOS Process

As the gate length of MOSFETs transistor is scaled down to 90 nm,the current driving ability of MOSFETs is degraded seriously and the leakage phenomenon becomes more and more serious.Therefore,it is an inefficient method to improve the performance by reducing the device size.As an efficient performance booster,silicon stress engineering can significantly enhance the driving current of devices by increasing carriers' mobility,and thus has been widely used in nanoscale devices below 90 nm technology node.Based on the 45 nm standard CMOS process,this thesis mainly studied the process realization and device physics of the stress memory technology(SMT)and the embedded SiGe source/drain technology(eSiGe S/D).The new stress enhancement methods and the optimized stress process conditions were explored to improve the performance of MOSFETs.The main innovative results are as follows:(1)The process realization of NFET device based on gate stress memory technique(SMT2)was studied.The effects of deposition temperature and post-treatment process of SiN film on the stress were further analyzed.A new method of synthesizing low temperature SiN deposition,ultraviolet light(UV)curing and high temperature rapid thermal annealing(RTA)was proposed to maximize the stress of SiN film,which increases the driving current and reduces the turn-off current of NFET devices with SMT2.By comparing experimental results under 300?,350?,400? and 480? deposition temperature,we found that the SiN film with low deposition temperature has porous property.In the subsequent high temperature rapid thermal annealing process,H atoms can more easily precipitate from SiN film.As a result,the content of residual H in SiN film is reduced and the stress of SiN film is thus enhanced.On the other hand,it was found that UV curing can break the Si-H and N-H bonds in the SiN film and the Si-N bonds can be regenerated.The stress of SiN can be further enhanced by subsequent high temperature rapid thermal annealing.The experimental results show that the SiN film deposited at a lower temperature of 300 ?,followed by UV curing and rapid thermal annealing can obtain the high stress of 1.7 GPa.At Vdd=1 V and Ioff=100 nA/?m,the maximum driving current of NFET is up to Ion=850 ?A/?m.The avarage driving current is about 10%higher than that of NFET device with SiN film deposited at 480?.(2)The process realization of NFET device based on source/drain stress memory technique(SMT1)was studied.A new method of growing a SiO2 buffer layer prior to SiN deposition was proposed.It not only enhances the stress of SiN film,but also reduces the damage caused by direct SiN deposition on the silicon surface,reducing the substrate leakage current of the device.The experimental results show that by optimizing the deposition temperature of SiN film,the driving current of NFET devices with buffer layer is increased by 5%compared with that of SMT1 NFET devices without buffer layer.Using this new buffer layer SMT1 technology,the driving current of traditional NFET devices without any stress technique can be improved by 11%.It is also experimentally found that the low temperature annealing should be adopted after SiN deposition in SMT1 process.However,excessive annealing will lead to release of stress and decrease of electron mobility,reducing the driving current gain.The 550? low temperature furnace annealing can meet the stress requirement of SMT1 and the maximum SMT1 stress can be obtained with 10 minutes annealing.On the other hand,the tensile stress of SiN film is introduced into the channel,which results in the degradation of PFET performance.A new method of selective Ge ions implantation into SiN film covered on PFET devices was proposed.The Si-N bonds cam be destroyed by the physical bombardment effect of Ge ions implantation,and thus the influence of SiN stress on PFET devices is reduced.The experimental results illustrate that the stress of SiN film is reduced by 27%after UV curing.Compared with the traditional selective etching SiN process for PFET device,this simple method can achieve low cost advantage.(3)The realization of Ni silicide process for embedded SiGe S/D PFET devices and the physical mechanism of device performance degradation were studied.A new Ni silicide process based on the combination of Si cap layer and pre amorphization implantation(PAI)is proposed,which improves the reliability of eSiGe S/D PFET devices significantly.It is known that the traditional Ni salicide process increases the leakage current of p+(SiGe)-n(Si)junction and the source/drain series resistance.Comparing the experimental results of four silicide processes such as Ni-only,Ni-PAI,Ni-Si cap and Ni-PAI-Si cap,it was found that the high BTBT electric field of drain/substrate junction and the agglomeration phenomenon of NiSiGe film lead to the increase of leakage current and the NiSi/SiGe interface roughness due to the local agglomeration of NiSiGe film also results into the increase of device source/drain series resistance.It was experimentally found that the addition of a Si cap layer in the Ni salicide process can reduce the drain/substrate junction leakage and the adding PAI(Ni-PAI)into the traditional Ni silicide process can make the silicide surface become very smooth and uniform,significantly reducing the bulk resistance of silicide film.The experimental results demonstrate that this new Ni silicide process combined with PAI and Si cap layer,not only reduces the junction leakage current by about one order of magnitude,but also lowers the source/drain series resistance from 70 ?/? to 16 ?/?.In addition,the decrease of source/drain series resistance and the increase of hole mobility also improve the saturation driving current IDS(sat)of PFET devices by 20%.