Research On Generation And Optimization Method Of Boundary Scan Test Vector For Complex Circuits

With the development of electronic technology,the traditional test method can not solve the problem of fault diagnosis of increasingly complex electronic circuit systems.Interconnect testing plays a very important role in circuit fault diagnosis,and the emergence of boundary scan makes interconnect testing more convenient,and can quickly and accurately detect and locate interconnect faults.The research focus and difficulty of boundary scan technology is to generate test vector generation algorithm for complex circuits.At present,the conventional interconnect diagnostic algorithm is difficult to balance the test time and fault diagnosis ability for complex circuit test,and most algorithms are optimized for a single indicator.Besides,the algorithm does not make efficient use of object structure information for optimization.There are two important indicators for judging the performance of a test generation algorithm for interconnect testing.They are the completeness index and the compactness index,the completeness index stand for the ability of fault diagnosis and the compactness index stand for test time.This paper will optimal the existing algorithm combine with the board structure information.The optimization goal is to ensure that the compactness index is as small as possible while ensuring that the completeness index is optimal.The main research content divide into the following four parts:1.Research on existing conventional test vector generation algorithms.This paper introduces the implementation of several existing conventional generation algorithms of test vector,and analyzes the performance of existing algorithms with its completeness index and compactness index.2.Research on test vector generation algorithm based on heuristic optimization grouping.This paper analyzes the performance and application difficulties of GNS algorithm,which is one of the existing conventional algorithms,and optimize the confusing condition of the algorithm.The step-by-step test mothod based on GNS algorithm is proposed in order to solve the above problems,and a heuristic optimization grouping GNS algorithm based on the circuit board structure information is proposed.The latter algorithm optimize the group formation by establishing interconnection network topology mosels in order to improving the performance.3.Test vector auto-generated research.In this paper,the automatic generation of the test vector depends on three kinds of simulation file,including netlist file,PCB report file and BSDL file.According to the compilation and analysis of the above text information,all relevant information of interconnection network and pins can be obtained,so that the automatic generation of test vectors can be realized based on the optimization algorithm proposed in this paper.4.Design and implementation of test vector automatic generation software.The software divede into three modules as following: text information analysis and compilation module,test vector automatic generation module and result analysis display module,and verify the software function and algorithm performance through comparative experiments.