Testability Analysis On Complex Digital Circuit Board Based On Boundary Scan Technology

As a standard DFT method, IEEE 1149.1 boundary-scan technique (BST) provides measures to complex interconnect test and can well make up the shortcoming of traditional test techniques. Nowadays most complex ICs are supporting IEEE 1149.1 test features. It should be considered by the hardware designer that how to use these ICs to achieve a better testability and higher fault coverage.With the central resource board in a common fault diagnosis system as the testing subject and based on systematic researches of BST, the paper has combined DFT theory to improve the board's structure and introduced boundary scan into circuit design. In the process, a test platform based on ScanWorks (by ASSET company) is built up; the logic models of devices are set up; and then test experiments on target boards are done. In this way the scan chain integrity test, boundary scan interconnect test and cluster test are accomplished, which has proved the effectiveness of DFT successfully. The current condition is that boundary scan and non-boundary scan devices will coexist in the actual applications for a long time. With this consideration and researches on the problems in the testing process, the paper has studied how to improve the observability and controllability of boundary scan devices over non-boundary scan devices to enhance its coverage of fault diagnosis. At last the results are proved through experiments.