A Study Of FPGA Protection Methods For Alleviating The Influence Of Soft Errors

Since its emergence, SRAM-based FPGA had been heading for a large-scale, high-density and low-power one and has reached the million gates of the Virtex-7 series. Great emphasis has been putting on it in the onboard equipment with these advantages. However, the logic gate circuits of its FPGA are loading to the SRAM dynamically and the proportion of the configuration bit in the memory cell of FPGA is more than 99%. Under a radiation environment, SRAM-based FPGA is more vulnerable to single-event, particularly the single-event upset(SEU), compared with ASIC and anti-fuse FPGA. Therefore, the way to improve the reliability of anti-SEU of a device has been a problem which should be specially considered in the design of a SRAM-based FPGA system.This thesis models the protection effect and cost of the common protection methods, followed by a theoretical analysis and a data analysis, which can offer a reference for choosing the protection method in engineering practice we expect. We conclude the main work of this thesis as follows.1. We abstract the radiation of the space high-energy particle to devices the Poisson Process, based on which, a theoretical derivation of the common protection methods for anti-SEU, such as triple modular redundancy protection method, refresh cycle protection method and hamming code protection method, is obtained. We also have a qualitative comparison of the reliability of anti-SEU with some protection and without any protection.2. It costs too much if a single protection method is applied to a whole FPGA project. Therefore, we divide it into some independent integrated mapping modules according to some rule and analyze the reliability of anti-SEU for each module. Protections are applied to the error-prone module, in order to achieve a maximal rise of performance with a minimum cost. Hence, a FPGA project is divided into modules according to some rule, for each module we implement the following five protection methods, module-based triple modular redundancy protection method, module-based time redundancy protection method improving reliability at the expense of speed, cycle refresh protection method re-erasing FPGA at an equal time interval, module-based refresh triple modular redundancy protection method combining cycle refresh and triple modular redundancy to improve reliability, hamming code protection method protecting BRAM.3. A quantitative analysis of performance for these protection methods is made in this thesis. And we analyze how much it will cost in terms of area, speed and power with the combination of the characteristics of FPGA. Through the analysis of experimental data of XC4VSX55 FPGA, we find it is in accordance with the prediction result of the theoretical model, which can offer some reference for choosing a protection method in engineering application...