Analysis Of Signal Reflection In GaAs-Based Ultra-High-Speed Folding-Interpolating ADC

Over the last 50 years, the technology of semiconductor has been progressing with Moore's Law, and with the rapid development of communication and digital signal processing technology, the demand for clock frequency in integrated circuit gets higher and higher, along with the problem that signal integrity cannot be ignored any more. Signal reflection widely exists in high speed and very high speed circuits and affects the function and performance of the circuits. It is one of the basic problems of signal integrity.Compared with the traditional CMOS technology based on silicon, Ga As HBT has a wider band gap, higher carrier saturation velocity, higher electron mobility and higher cut-off frequency, which is more suitable for the design of High Speed and Very High Speed Integrated Circuits. The signal reflection exists in many paths in the very high speed mixed-signal integrated circuits which based on Ga As HBT. The mechanism of signal reflection and ways to improve the signal quality were studied in this thesis by using the 3Gbps 6bits folding-interpolating ADC as an example.Based on the analysis of the signal and interconnects, we can determine if the signal integrity exists in the circuit, this thesis presents the way to get delay of interconnects. The method to get the characteristic impedance by using ADS momentum with technology file is presented in this thesis. Interconnects can be terminated with knowing the characteristic impedance. For interconnects in ADC, parallel RC termination is adopted and the simulation result shows that the noise caused by signal reflection can be controlled within 10 percent.Besides, some other structures in the ADC that cause impedance discontinuities are analyzed and we can get some conclusions that can guide the design of the layout. For the bend of interconnects, we should use the arc bend. The impedance of a larger via is closer to the characteristic impedance of interconnects, and the delay of via degrades the signal quality. For different interconnects, the shorter one contributes less in the entire impedance. These conclusions can be used in handling the structures which cause impedance discontinuities.In the specific ADC circuit, the place of layout is determined first. We choose the appropriate topology after that, and use different ways to alleviate the impedance discontinuities in topology to minimize the signal reflection in every part of the circuit. The simulation of the entire circuit shows the effectiveness and correctness of the strategy.