Timing Degradation Analysis Of Radiation Combined Effect On Space Digital Circuit

With the development of Moore`s Law, the process node of digital integrated circuit has reached VDSM. The long-term reliability problems of transistor are changing from the Time Dependent Dielectric Breakdown and the Electrical Migration to the Negative Bias Temperature Instability and the Channel Hot Carrier effect. Along with the gradually penetrating research of space exploration, the combination of Total Ionizing Dose effect and Channel Hot Carrier effect shows that 1+1>2. For transistor, these three device effects bring an increase in the absolute value of the threshold voltage. For digital circuits, the increase of threshold voltage will result in an increase in circuit delay and cause timing issues. The key point of reliability design is how to complete the cross layer modeling from device-level mechanism to the transistor level modeling and then to circuit-level timing analysis. For this purpose, the following work has been done on the CMOS 130 nm process:In this paper, the physical mechanism of NBTI effect, CHC effect and TID effect and the classical interpretation models of these three effects are introduced. From latest academic research results and considering the actual work of digital circuit, we have introduced the transistor level models, including NBTI, TID and CHC long-term dynamic model, which are based on the duty ratio, as a variable. To work for ten years as the target, we have calculated the voltage shift range for PMOS at 50 m V~73m V which caused by the NBTI effect and NMOS at 77 m V~220m V which caused by the CHC and TID combinative effects.In this paper, we use 16×16 shift multiplier`s RTL codes as the object of aging analysis. Through setting timing and area constraints, we complete the logic synthesis in Design Complier, and get the critical path from static timing analysis?After completing the floorplan, clock tree synthesis and rout in Encounter, we have obtained the layout and the timing variation of the critical path after physical design.In view of the duty ratio as variable which changes threshold, the mutative law of timing margin is analyzed in this paper. This article chooses the one time drive inverter, two input nand gate and two input nor gate as the research objects, and gives the relationship between duty ratio and the circuit delay. After obtaining the critical path based on the static timing analysis, we establish aging timing library of the combinational logic standard cell in the critical path. On the basis of aging timing library, we complete logic synthesis in DC tool and place & route in Encounter again, and get the variation of circuit delay. For the critical path, the timing delay of the combinational logic increases 1.61 ns in the logic synthesis step, and which becomes 2.159 ns after the place & route step, nearly 10%. So we get a reasonable result for anti-aging and frequency decrease using.