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Research On NBTI In Ultra Deep Sub Micron PMOSFET Device

Posted on:2009-01-31Degree:MasterType:Thesis
Country:ChinaCandidate:Y HuangFull Text:PDF
GTID:2178360242491834Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
This thesis mainly investigates the NBTI degradation phenomena and mechanism in Ultra-deep submicron PMOSFET. Based on the software platform Virtuoso, layout of NBTI test chips are designed, and joined 0.18μm 1P6M CMOS MPW flow in HEJIAN; a lot of references at home and abroad are read, and NBTI test project is designed finally, then some problems about NBTI test method are deeply discussed; on the analysis of test results, failure mode and failure mechanism, NBTI lifetime factors, couple effects of NBTI and HCI are researched, reliability lifetime evaluation for NBTI effect and the couple effects of NBTI and HCI are finished at last.Using the NBTI test chip and test project, the influence on PMOSFET device characteristics and parameters by NBTI effect, various device parameters shift vs. NBTI stress time and the influence on threshold voltage shift△Vth by PMOSFET device parameters are analyzed, research indicate that parameters of PMOSFET can be shifted continually and device I-V characteristics grow worsen, the shift of different device parameters followed the power-law relationship (n = 0.27~0.29) with NBT stress time, Vth has the maximum shifts and need to act as key parameter for lifetime prediction. The increase of NBT stress and the scaling of PMOSFET device structure parameters both make△Vth worse.Using△Vth as the criterion of device lifetime evaluation, research indicate that PMOSFET NBTI lifetime have relationship with stress time t, stress temperature T, negative gate voltage Vgs, channel width W and channel length L. Based on test measure results,△Vth lifetime evaluation expression is gotten, which can predict device lifetime by NBTI effect.Based on a lot of experiments for couple effects of NBTI and HCI, research indicate that the degradation slopes of Vth and Idsat with stress time are bigger than slopes under NBT stress alone, which means the degradation of device parameters are caused by both NBTI and HCI mechanism. Making use of characteristics of△Vth has no relationship with channel length L, the contribution of HCI effect for△Vth under NBT+HCI stress is decomposed. Making use of characteristics of△Vth has linear relationship with %I)dsat under NBT+HCI stress, using Idsat as the evaluation criterion, the couple effects of NBTI and HCI lifetime evaluation expression is gotten.
Keywords/Search Tags:reliability, lifetime evaluation, NBTI, HCI, threshold voltage
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