The Research On Technique Of Digital Integrated Circuit Aging Prediction And Defection

As transistor technology dimension declines, the integration of digital circuits is increasingly higher and the performance of the circuits becomes better at the same time. While, circuits aging becomes one of the leading factors affecting the reliability of the circuits. During the later half of IC lifetime, aging directly leads to timing violation or even permanent failure.In this paper, research about circuits aging mainly includes following two aspects:(1) According to one physical mechanism of Negative Bias Temperature Instability (NBTI) effect, a gate delay prediction model is presented fors setting the timing margin of the ciscuits. (2) Considering the reliability of heterogeneous Multiprocessor System-on-Chip (MPSoC) under the influence of Electromigration effect, a kind of task scheduling algorithm named cross is put forward to improve the reliability of heterogeneous MPSoC.For guaranteeing the validity of digital circuits during the lifetime, some certain measures should be taken to help circuits adapt to aging effects. Commonly, a protective solution is to set a certain amount of timing margin for some critical paths at the stage of IC design. But an accurate aging prediction model is important to guaranteeing a sure lifetime of the circuit. There are several effective aging effects along with the technology getting into the nano-scale, NBTI turn out to be the most leading aging factors causing wear-out. Aimming at preventing the reliability from NBTI effect, NBTI-based timing margin is an important technique. While, NBTI-based timing margin needs corrective NBTI-based aging prediction model. Currently, the aging prediction model based on NBTI Reaction-Diffusion mechanism is the mainstream model, which shows that the reliability measurement (gate delay) has an exponential function with circuit working time. In this paper, a novel aging forecasting model named Trapping/Detrapping-based Delay Prediction (TDDP) is established by considering NBTI hole Trapping/Detrapping mechanism. This model gives that gate delay has a logarithmic function with circuits working time. After building up TDDP, the calculation results of TDDP is compared with the results of Hspice simulation tools and accuracy deviations is within the tolerance range. Experimental results demonstrates that TDDP model is also more suitable to setting timing margin compared to the Reaction Diffusion based delay prediction model.With the wide application of Multiprocessor System-on-Chip (MPSoC), digital IC aging effects bring great challenge to the reliability of MPSoC. The higher interconnection density of MPSoC causing that Electromigration (EM) effect becomes a larger threaten to the reliability of MPSoC. Based on the Mean Time to Failure (MTTF) model of a single processor under EM effect, a target optimization model for a heterogeneous MPSoC is concluded. Then, a MTTF-aware task scheduling algorithm named cross is suggested for achieving the goal of reducing the reliability diversity of heterogeneous MPSoC. Frequency heterogeneity leads to inherent diversity of reliability of each processor. Cross is a task scheduling algorithm considering processor reliability diversity. Experimental results prove that cross has positive impact on the reliability guarantee of heterogeneous of MPSoC compared with exsiting workload balance algorithm.